[llvm-commits] CVS: llvm/lib/Target/ARM/ARMMachineFunctionInfo.h ARMRegisterInfo.cpp

[Evan Cheng]

Changes in directory llvm/lib/Target/ARM:

ARMMachineFunctionInfo.h updated: 1.3 -> 1.4
ARMRegisterInfo.cpp updated: 1.42 -> 1.43
---
Log message:

Remember if LR register has been spilled in this function.

---
Diffs of the changes:  (+17 -5)

 ARMMachineFunctionInfo.h |   16 ++++++++++++----
 ARMRegisterInfo.cpp      |    6 +++++-
 2 files changed, 17 insertions(+), 5 deletions(-)


Index: llvm/lib/Target/ARM/ARMMachineFunctionInfo.h
diff -u llvm/lib/Target/ARM/ARMMachineFunctionInfo.h:1.3 
llvm/lib/Target/ARM/ARMMachineFunctionInfo.h:1.4
--- llvm/lib/Target/ARM/ARMMachineFunctionInfo.h:1.3    Wed Jan 24 21:07:27 2007
+++ llvm/lib/Target/ARM/ARMMachineFunctionInfo.h        Mon Jan 29 16:22:24 2007
@@ -36,6 +36,10 @@
   /// processFunctionBeforeCalleeSavedScan().
   bool HasStackFrame;
 
+  /// LRSpilled - True if the LR register has been spilled.
+  ///
+  bool LRSpilled;
+
   /// FramePtrSpillOffset - If HasStackFrame, this records the frame pointer
   /// spill stack offset.
   unsigned FramePtrSpillOffset;
@@ -71,14 +75,14 @@
 public:
   ARMFunctionInfo() :
     isThumb(false),
-    VarArgsRegSaveSize(0), HasStackFrame(false), FramePtrSpillOffset(0),
-    GPRCS1Offset(0), GPRCS2Offset(0), DPRCSOffset(0),
+    VarArgsRegSaveSize(0), HasStackFrame(false), LRSpilled(false),
+    FramePtrSpillOffset(0), GPRCS1Offset(0), GPRCS2Offset(0), DPRCSOffset(0),
     GPRCS1Size(0), GPRCS2Size(0), DPRCSSize(0), JumpTableUId(0) {}
 
   ARMFunctionInfo(MachineFunction &MF) :
     isThumb(MF.getTarget().getSubtarget<ARMSubtarget>().isThumb()),
-    VarArgsRegSaveSize(0), HasStackFrame(false), FramePtrSpillOffset(0),
-    GPRCS1Offset(0), GPRCS2Offset(0), DPRCSOffset(0),
+    VarArgsRegSaveSize(0), HasStackFrame(false), LRSpilled(false),
+    FramePtrSpillOffset(0), GPRCS1Offset(0), GPRCS2Offset(0), DPRCSOffset(0),
     GPRCS1Size(0), GPRCS2Size(0), DPRCSSize(0), JumpTableUId(0) {}
 
   bool isThumbFunction() const { return isThumb; }
@@ -88,6 +92,10 @@
 
   bool hasStackFrame() const { return HasStackFrame; }
   void setHasStackFrame(bool s) { HasStackFrame = s; }
+
+  bool isLRSpilled() const { return LRSpilled; }
+  void setLRIsSpilled(bool s) { LRSpilled = s; }
+
   unsigned getFramePtrSpillOffset() const { return FramePtrSpillOffset; }
   void setFramePtrSpillOffset(unsigned o) { FramePtrSpillOffset = o; }
   


Index: llvm/lib/Target/ARM/ARMRegisterInfo.cpp
diff -u llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.42 
llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.43
--- llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.42        Fri Jan 26 15:33:19 2007
+++ llvm/lib/Target/ARM/ARMRegisterInfo.cpp     Mon Jan 29 16:22:24 2007
@@ -769,13 +769,14 @@
     }
   }
 
+  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
   if (!CanEliminateFrame) {
-    ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
     AFI->setHasStackFrame(true);
 
     // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.
     // Spill LR as well so we can fold BX_RET to the registers restore (LDM).
     if (!LRSpilled && CS1Spilled) {
+      LRSpilled = true;
       MF.changePhyRegUsed(ARM::LR, true);
       NumGPRSpills++;
       UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(),
@@ -798,6 +799,9 @@
         MF.changePhyRegUsed(UnspilledCS2GPRs.front(), true);
     }
   }
+
+  // Remembe if LR has been spilled.
+  AFI->setLRIsSpilled(LRSpilled);
 }
 
 /// Move iterator pass the next bunch of callee save load / store ops for



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