Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.362 -> 1.363 X86InstrMMX.td updated: 1.15 -> 1.16 --- Log message: Properly support v8i8 and v4i16 types. It now converts them to v2i32 for load and stores. --- Diffs of the changes: (+20 -6) X86ISelLowering.cpp | 7 +++++-- X86InstrMMX.td | 19 +++++++++++++++---- 2 files changed, 20 insertions(+), 6 deletions(-) Index: llvm/lib/Target/X86/X86ISelLowering.cpp diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.362 llvm/lib/Target/X86/X86ISelLowering.cpp:1.363 --- llvm/lib/Target/X86/X86ISelLowering.cpp:1.362 Tue Mar 6 12:53:42 2007 +++ llvm/lib/Target/X86/X86ISelLowering.cpp Tue Mar 6 23:43:18 2007 @@ -327,9 +327,12 @@ addRegisterClass(MVT::v2i32, X86::VR64RegisterClass); // FIXME: add MMX packed arithmetics - setOperationAction(ISD::LOAD, MVT::v8i8, Legal); - setOperationAction(ISD::LOAD, MVT::v4i16, Legal); + setOperationAction(ISD::LOAD, MVT::v8i8, Promote); + AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v2i32); + setOperationAction(ISD::LOAD, MVT::v4i16, Promote); + AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v2i32); setOperationAction(ISD::LOAD, MVT::v2i32, Legal); + setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Expand); setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Expand); setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Expand); Index: llvm/lib/Target/X86/X86InstrMMX.td diff -u llvm/lib/Target/X86/X86InstrMMX.td:1.15 llvm/lib/Target/X86/X86InstrMMX.td:1.16 --- llvm/lib/Target/X86/X86InstrMMX.td:1.15 Tue Mar 6 12:53:42 2007 +++ llvm/lib/Target/X86/X86InstrMMX.td Tue Mar 6 23:43:18 2007 @@ -1,4 +1,4 @@ -//====- X86InstrMMX.td - Describe the X86 Instruction Set -------*- C++ -*-===// +//====- X86InstrMMX.td - Describe the X86 Instruction Set --*- tablegen -*-===// // // The LLVM Compiler Infrastructure // @@ -33,14 +33,17 @@ [(set VR64:$dst, (v8i8 (undef)))]>, Requires<[HasMMX]>; -def : Pat<(v8i8 (undef)), (IMPLICIT_DEF_VR64)>, Requires<[HasMMX]>; -def : Pat<(v4i16 (undef)), (IMPLICIT_DEF_VR64)>, Requires<[HasMMX]>; -def : Pat<(v2i32 (undef)), (IMPLICIT_DEF_VR64)>, Requires<[HasMMX]>; +// 64-bit vector undef's. +def : Pat<(v8i8 (undef)), (IMPLICIT_DEF_VR64)>; +def : Pat<(v4i16 (undef)), (IMPLICIT_DEF_VR64)>; +def : Pat<(v2i32 (undef)), (IMPLICIT_DEF_VR64)>; //===----------------------------------------------------------------------===// // MMX Pattern Fragments //===----------------------------------------------------------------------===// +def loadv8i8 : PatFrag<(ops node:$ptr), (v8i8 (load node:$ptr))>; +def loadv4i16 : PatFrag<(ops node:$ptr), (v4i16 (load node:$ptr))>; def loadv2i32 : PatFrag<(ops node:$ptr), (v2i32 (load node:$ptr))>; //===----------------------------------------------------------------------===// @@ -120,3 +123,11 @@ (MOVQ64mr addr:$dst, VR64:$src)>; def : Pat<(store (v4i16 VR64:$src), addr:$dst), (MOVQ64mr addr:$dst, VR64:$src)>; + +// Bit convert. +def : Pat<(v8i8 (bitconvert (v2i32 VR64:$src))), (v8i8 VR64:$src)>; +def : Pat<(v8i8 (bitconvert (v4i16 VR64:$src))), (v8i8 VR64:$src)>; +def : Pat<(v4i16 (bitconvert (v2i32 VR64:$src))), (v4i16 VR64:$src)>; +def : Pat<(v4i16 (bitconvert (v8i8 VR64:$src))), (v4i16 VR64:$src)>; +def : Pat<(v2i32 (bitconvert (v4i16 VR64:$src))), (v2i32 VR64:$src)>; +def : Pat<(v2i32 (bitconvert (v8i8 VR64:$src))), (v2i32 VR64:$src)>; _______________________________________________ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits