Changes in directory llvm/lib/Target/ARM:
ARMRegisterInfo.cpp updated: 1.93 -> 1.94 --- Log message: Fix PR1390: http://llvm.org/PR1390 . Don't spill extra register to align the stack. --- Diffs of the changes: (+10 -38) ARMRegisterInfo.cpp | 48 ++++++++++-------------------------------------- 1 files changed, 10 insertions(+), 38 deletions(-) Index: llvm/lib/Target/ARM/ARMRegisterInfo.cpp diff -u llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.93 llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.94 --- llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.93 Thu May 3 15:28:35 2007 +++ llvm/lib/Target/ARM/ARMRegisterInfo.cpp Sat May 5 18:44:41 2007 @@ -1131,26 +1131,6 @@ NumGPRSpills++; } - // If stack and double are 8-byte aligned and we are spilling an odd number - // of GPRs. Spill one extra callee save GPR so we won't have to pad between - // the integer and double callee save areas. - unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); - if (TargetAlign == 8 && (NumGPRSpills & 1)) { - if (CS1Spilled && !UnspilledCS1GPRs.empty()) { - unsigned Reg = UnspilledCS1GPRs.front(); - MF.setPhysRegUsed(Reg); - AFI->setCSRegisterIsSpilled(Reg); - if (!isReservedReg(MF, Reg)) - ExtraCSSpill = true; - } else if (!UnspilledCS2GPRs.empty()) { - unsigned Reg = UnspilledCS2GPRs.front(); - MF.setPhysRegUsed(Reg); - AFI->setCSRegisterIsSpilled(Reg); - if (!isReservedReg(MF, Reg)) - ExtraCSSpill = true; - } - } - // Estimate if we might need to scavenge a register at some point in order // to materialize a stack offset. If so, either spill one additiona // callee-saved register or reserve a special spill slot to facilitate @@ -1180,29 +1160,26 @@ if (Size >= Limit) { // If any non-reserved CS register isn't spilled, just spill one or two // extra. That should take care of it! - unsigned NumExtras = TargetAlign / 4; - SmallVector<unsigned, 2> Extras; - while (NumExtras && !UnspilledCS1GPRs.empty()) { + unsigned Extra; + while (!ExtraCSSpill && !UnspilledCS1GPRs.empty()) { unsigned Reg = UnspilledCS1GPRs.back(); UnspilledCS1GPRs.pop_back(); if (!isReservedReg(MF, Reg)) { - Extras.push_back(Reg); - NumExtras--; + Extra = Reg; + ExtraCSSpill = true; } } - while (NumExtras && !UnspilledCS2GPRs.empty()) { + while (!ExtraCSSpill && !UnspilledCS2GPRs.empty()) { unsigned Reg = UnspilledCS2GPRs.back(); UnspilledCS2GPRs.pop_back(); if (!isReservedReg(MF, Reg)) { - Extras.push_back(Reg); - NumExtras--; + Extra = Reg; + ExtraCSSpill = true; } } - if (Extras.size() && NumExtras == 0) { - for (unsigned i = 0, e = Extras.size(); i != e; ++i) { - MF.setPhysRegUsed(Extras[i]); - AFI->setCSRegisterIsSpilled(Extras[i]); - } + if (ExtraCSSpill) { + MF.setPhysRegUsed(Extra); + AFI->setCSRegisterIsSpilled(Extra); } else { // Reserve a slot closest to SP or frame pointer. const TargetRegisterClass *RC = &ARM::GPRRegClass; @@ -1263,7 +1240,6 @@ ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); bool isThumb = AFI->isThumbFunction(); unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize(); - unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); unsigned NumBytes = MFI->getStackSize(); const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); @@ -1330,10 +1306,6 @@ } } - if (Align == 8 && (GPRCS1Size & 7) != 0) - // Pad CS1 to ensure proper alignment. - GPRCS1Size += 4; - if (!isThumb) { // Build the new SUBri to adjust SP for integer callee-save spill area 1. emitSPUpdate(MBB, MBBI, -GPRCS1Size, isThumb, TII); _______________________________________________ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits