Author: evancheng
Date: Fri Jul 13 18:55:50 2007
New Revision: 39843
URL: http://llvm.org/viewvc/llvm-project?rev=39843&view=rev
Log:
Fix for PR1540: Specify F0, F1 are sub-registers of D0, etc.
Modified:
llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.td
Modified: llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.td?rev=39843&r1=39842&r2=39843&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.td (original)
+++ llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.td Fri Jul 13 18:55:50 2007
@@ -26,9 +26,9 @@
let Num = num;
}
// Rd - Slots in the FP register file for 64-bit floating-point values.
-class Rd<bits<5> num, string n, list<Register> aliases> : SparcReg<n> {
+class Rd<bits<5> num, string n, list<Register> subregs> : SparcReg<n> {
let Num = num;
- let Aliases = aliases;
+ let SubRegs = subregs;
}
// Integer registers
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