Author: djg Date: Fri Sep 14 15:33:02 2007 New Revision: 41958 URL: http://llvm.org/viewvc/llvm-project?rev=41958&view=rev Log: Remove isReg, isImm, and isMBB, and change all their users to use isRegister, isImmediate, and isMachineBasicBlock, which are equivalent, and more popular.
Modified: llvm/trunk/include/llvm/CodeGen/LiveVariables.h llvm/trunk/include/llvm/CodeGen/MachineInstr.h llvm/trunk/lib/CodeGen/AsmPrinter.cpp llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp llvm/trunk/lib/CodeGen/LiveVariables.cpp llvm/trunk/lib/CodeGen/LowerSubregs.cpp llvm/trunk/lib/CodeGen/MachineInstr.cpp llvm/trunk/lib/CodeGen/RegisterScavenging.cpp llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp llvm/trunk/lib/CodeGen/VirtRegMap.cpp llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp llvm/trunk/lib/Target/PowerPC/PPCBranchSelector.cpp llvm/trunk/lib/Target/TargetInstrInfo.cpp llvm/trunk/lib/Target/X86/X86ATTAsmPrinter.cpp llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Modified: llvm/trunk/include/llvm/CodeGen/LiveVariables.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/LiveVariables.h?rev=41958&r1=41957&r2=41958&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/LiveVariables.h (original) +++ llvm/trunk/include/llvm/CodeGen/LiveVariables.h Fri Sep 14 15:33:02 2007 @@ -229,7 +229,7 @@ bool Removed = false; for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { MachineOperand &MO = MI->getOperand(i); - if (MO.isReg() && MO.isKill() && MO.getReg() == reg) { + if (MO.isRegister() && MO.isKill() && MO.getReg() == reg) { MO.unsetIsKill(); Removed = true; break; @@ -266,7 +266,7 @@ bool Removed = false; for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { MachineOperand &MO = MI->getOperand(i); - if (MO.isReg() && MO.isDef() && MO.getReg() == reg) { + if (MO.isRegister() && MO.isDef() && MO.getReg() == reg) { MO.unsetIsDead(); Removed = true; break; Modified: llvm/trunk/include/llvm/CodeGen/MachineInstr.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineInstr.h?rev=41958&r1=41957&r2=41958&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineInstr.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineInstr.h Fri Sep 14 15:33:02 2007 @@ -131,10 +131,6 @@ /// Accessors that tell you what kind of MachineOperand you're looking at. /// - bool isReg() const { return opType == MO_Register; } - bool isImm() const { return opType == MO_Immediate; } - bool isMBB() const { return opType == MO_MachineBasicBlock; } - bool isRegister() const { return opType == MO_Register; } bool isImmediate() const { return opType == MO_Immediate; } bool isMachineBasicBlock() const { return opType == MO_MachineBasicBlock; } @@ -145,12 +141,12 @@ bool isExternalSymbol() const { return opType == MO_ExternalSymbol; } int64_t getImm() const { - assert(isImm() && "Wrong MachineOperand accessor"); + assert(isImmediate() && "Wrong MachineOperand accessor"); return contents.immedVal; } int64_t getImmedValue() const { - assert(isImm() && "Wrong MachineOperand accessor"); + assert(isImmediate() && "Wrong MachineOperand accessor"); return contents.immedVal; } MachineBasicBlock *getMBB() const { @@ -257,11 +253,11 @@ } void setImmedValue(int64_t immVal) { - assert(isImm() && "Wrong MachineOperand mutator"); + assert(isImmediate() && "Wrong MachineOperand mutator"); contents.immedVal = immVal; } void setImm(int64_t immVal) { - assert(isImm() && "Wrong MachineOperand mutator"); + assert(isImmediate() && "Wrong MachineOperand mutator"); contents.immedVal = immVal; } Modified: llvm/trunk/lib/CodeGen/AsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter.cpp?rev=41958&r1=41957&r2=41958&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter.cpp Fri Sep 14 15:33:02 2007 @@ -982,7 +982,7 @@ // Count the number of register definitions. unsigned NumDefs = 0; - for (; MI->getOperand(NumDefs).isReg() && MI->getOperand(NumDefs).isDef(); + for (; MI->getOperand(NumDefs).isRegister() && MI->getOperand(NumDefs).isDef(); ++NumDefs) assert(NumDefs != NumOperands-1 && "No asm string?"); Modified: llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=41958&r1=41957&r2=41958&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp (original) +++ llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Fri Sep 14 15:33:02 2007 @@ -413,7 +413,7 @@ bool HasUse = mop.isUse(); bool HasDef = mop.isDef(); for (unsigned j = i+1, e = MI->getNumOperands(); j != e; ++j) { - if (MI->getOperand(j).isReg() && + if (MI->getOperand(j).isRegister() && MI->getOperand(j).getReg() == li.reg) { MI->getOperand(j).setReg(NewVReg); HasUse |= MI->getOperand(j).isUse(); Modified: llvm/trunk/lib/CodeGen/LiveVariables.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveVariables.cpp?rev=41958&r1=41957&r2=41958&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LiveVariables.cpp (original) +++ llvm/trunk/lib/CodeGen/LiveVariables.cpp Fri Sep 14 15:33:02 2007 @@ -78,7 +78,7 @@ bool LiveVariables::KillsRegister(MachineInstr *MI, unsigned Reg) const { for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { MachineOperand &MO = MI->getOperand(i); - if (MO.isReg() && MO.isKill()) { + if (MO.isRegister() && MO.isKill()) { if ((MO.getReg() == Reg) || (MRegisterInfo::isPhysicalRegister(MO.getReg()) && MRegisterInfo::isPhysicalRegister(Reg) && @@ -92,7 +92,7 @@ bool LiveVariables::RegisterDefIsDead(MachineInstr *MI, unsigned Reg) const { for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { MachineOperand &MO = MI->getOperand(i); - if (MO.isReg() && MO.isDead()) { + if (MO.isRegister() && MO.isDead()) { if ((MO.getReg() == Reg) || (MRegisterInfo::isPhysicalRegister(MO.getReg()) && MRegisterInfo::isPhysicalRegister(Reg) && @@ -106,7 +106,7 @@ bool LiveVariables::ModifiesRegister(MachineInstr *MI, unsigned Reg) const { for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { MachineOperand &MO = MI->getOperand(i); - if (MO.isReg() && MO.isDef() && MO.getReg() == Reg) + if (MO.isRegister() && MO.isDef() && MO.getReg() == Reg) return true; } return false; @@ -190,7 +190,7 @@ bool Found = false; for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { MachineOperand &MO = MI->getOperand(i); - if (MO.isReg() && MO.isUse()) { + if (MO.isRegister() && MO.isUse()) { unsigned Reg = MO.getReg(); if (!Reg) continue; @@ -221,7 +221,7 @@ bool Found = false; for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { MachineOperand &MO = MI->getOperand(i); - if (MO.isReg() && MO.isDef()) { + if (MO.isRegister() && MO.isDef()) { unsigned Reg = MO.getReg(); if (!Reg) continue; @@ -614,7 +614,7 @@ void LiveVariables::removeVirtualRegistersKilled(MachineInstr *MI) { for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { MachineOperand &MO = MI->getOperand(i); - if (MO.isReg() && MO.isKill()) { + if (MO.isRegister() && MO.isKill()) { MO.unsetIsKill(); unsigned Reg = MO.getReg(); if (MRegisterInfo::isVirtualRegister(Reg)) { @@ -630,7 +630,7 @@ void LiveVariables::removeVirtualRegistersDead(MachineInstr *MI) { for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { MachineOperand &MO = MI->getOperand(i); - if (MO.isReg() && MO.isDead()) { + if (MO.isRegister() && MO.isDead()) { MO.unsetIsDead(); unsigned Reg = MO.getReg(); if (MRegisterInfo::isVirtualRegister(Reg)) { Modified: llvm/trunk/lib/CodeGen/LowerSubregs.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LowerSubregs.cpp?rev=41958&r1=41957&r2=41958&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LowerSubregs.cpp (original) +++ llvm/trunk/lib/CodeGen/LowerSubregs.cpp Fri Sep 14 15:33:02 2007 @@ -66,7 +66,7 @@ assert(MI->getOperand(0).isRegister() && MI->getOperand(0).isDef() && MI->getOperand(1).isRegister() && MI->getOperand(1).isUse() && - MI->getOperand(2).isImm() && "Malformed extract_subreg"); + MI->getOperand(2).isImmediate() && "Malformed extract_subreg"); unsigned SuperReg = MI->getOperand(1).getReg(); unsigned SubIdx = MI->getOperand(2).getImm(); @@ -113,7 +113,7 @@ if (MI->getNumOperands() == 3) { assert((MI->getOperand(0).isRegister() && MI->getOperand(0).isDef()) && (MI->getOperand(1).isRegister() && MI->getOperand(1).isUse()) && - MI->getOperand(2).isImm() && "Invalid extract_subreg"); + MI->getOperand(2).isImmediate() && "Invalid extract_subreg"); DstReg = MI->getOperand(0).getReg(); SrcReg = DstReg; InsReg = MI->getOperand(1).getReg(); @@ -122,7 +122,7 @@ assert((MI->getOperand(0).isRegister() && MI->getOperand(0).isDef()) && (MI->getOperand(1).isRegister() && MI->getOperand(1).isUse()) && (MI->getOperand(2).isRegister() && MI->getOperand(2).isUse()) && - MI->getOperand(3).isImm() && "Invalid extract_subreg"); + MI->getOperand(3).isImmediate() && "Invalid extract_subreg"); DstReg = MI->getOperand(0).getReg(); SrcReg = MI->getOperand(1).getReg(); InsReg = MI->getOperand(2).getReg(); Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineInstr.cpp?rev=41958&r1=41957&r2=41958&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineInstr.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineInstr.cpp Fri Sep 14 15:33:02 2007 @@ -188,7 +188,7 @@ int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill) const { for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { const MachineOperand &MO = getOperand(i); - if (MO.isReg() && MO.isUse() && MO.getReg() == Reg) + if (MO.isRegister() && MO.isUse() && MO.getReg() == Reg) if (!isKill || MO.isKill()) return i; } @@ -200,7 +200,7 @@ MachineOperand *MachineInstr::findRegisterDefOperand(unsigned Reg) { for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { MachineOperand &MO = getOperand(i); - if (MO.isReg() && MO.isDef() && MO.getReg() == Reg) + if (MO.isRegister() && MO.isDef() && MO.getReg() == Reg) return &MO; } return NULL; @@ -225,7 +225,7 @@ void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) { for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { const MachineOperand &MO = MI->getOperand(i); - if (!MO.isReg() || (!MO.isKill() && !MO.isDead())) + if (!MO.isRegister() || (!MO.isKill() && !MO.isDead())) continue; for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) { MachineOperand &MOp = getOperand(j); @@ -248,7 +248,7 @@ if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND)) { const MachineOperand &MO = MI->getOperand(i); // Predicated operands must be last operands. - if (MO.isReg()) + if (MO.isRegister()) addRegOperand(MO.getReg(), false); else { addImmOperand(MO.getImm()); @@ -319,7 +319,7 @@ unsigned StartOp = 0; // Specialize printing if op#0 is definition - if (getNumOperands() && getOperand(0).isReg() && getOperand(0).isDef()) { + if (getNumOperands() && getOperand(0).isRegister() && getOperand(0).isDef()) { ::print(getOperand(0), OS, TM); if (getOperand(0).isDead()) OS << "<dead>"; @@ -337,7 +337,7 @@ OS << " "; ::print(mop, OS, TM); - if (mop.isReg()) { + if (mop.isRegister()) { if (mop.isDef() || mop.isKill() || mop.isDead() || mop.isImplicit()) { OS << "<"; bool NeedComma = false; @@ -381,7 +381,7 @@ for (unsigned i = 0, N = getNumOperands(); i < N; i++) { os << "\t" << getOperand(i); - if (getOperand(i).isReg() && getOperand(i).isDef()) + if (getOperand(i).isRegister() && getOperand(i).isDef()) os << "<d>"; } Modified: llvm/trunk/lib/CodeGen/RegisterScavenging.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterScavenging.cpp?rev=41958&r1=41957&r2=41958&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegisterScavenging.cpp (original) +++ llvm/trunk/lib/CodeGen/RegisterScavenging.cpp Fri Sep 14 15:33:02 2007 @@ -102,7 +102,7 @@ BitVector ChangedRegs(NumPhysRegs); for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { const MachineOperand &MO = MI->getOperand(i); - if (!MO.isReg() || !MO.isUse()) + if (!MO.isRegister() || !MO.isUse()) continue; unsigned Reg = MO.getReg(); if (Reg == 0) @@ -125,7 +125,7 @@ const TargetInstrDescriptor *TID = MI->getInstrDescriptor(); for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { const MachineOperand &MO = MI->getOperand(i); - if (!MO.isReg() || !MO.isDef()) + if (!MO.isRegister() || !MO.isDef()) continue; unsigned Reg = MO.getReg(); // If it's dead upon def, then it is now free. @@ -155,7 +155,7 @@ const TargetInstrDescriptor *TID = MI->getInstrDescriptor(); for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { const MachineOperand &MO = MI->getOperand(i); - if (!MO.isReg() || !MO.isDef()) + if (!MO.isRegister() || !MO.isDef()) continue; // Skip two-address destination operand. if (TID->findTiedToSrcOperand(i) != -1) @@ -170,7 +170,7 @@ BitVector ChangedRegs(NumPhysRegs); for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { const MachineOperand &MO = MI->getOperand(i); - if (!MO.isReg() || !MO.isUse()) + if (!MO.isRegister() || !MO.isUse()) continue; unsigned Reg = MO.getReg(); if (Reg == 0) @@ -257,7 +257,7 @@ // Exclude all the registers being used by the instruction. for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) { MachineOperand &MO = I->getOperand(i); - if (MO.isReg()) + if (MO.isRegister()) Candidates.reset(MO.getReg()); } Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp?rev=41958&r1=41957&r2=41958&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp (original) +++ llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Fri Sep 14 15:33:02 2007 @@ -986,7 +986,7 @@ for (unsigned i = 0, NumOps = MI->getNumOperands(); i != NumOps; ++i) { MachineOperand &MO = MI->getOperand(i); - if (MO.isReg() && MO.isUse() && MO.getReg() && + if (MO.isRegister() && MO.isUse() && MO.getReg() && mri_->regsOverlap(rep(MO.getReg()), Reg)) { MOU = &MO; return MI; @@ -1005,7 +1005,7 @@ MachineOperand *SimpleRegisterCoalescing::findDefOperand(MachineInstr *MI, unsigned Reg) { for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { MachineOperand &MO = MI->getOperand(i); - if (MO.isReg() && MO.isDef() && + if (MO.isRegister() && MO.isDef() && mri_->regsOverlap(rep(MO.getReg()), Reg)) return &MO; } @@ -1017,7 +1017,7 @@ void SimpleRegisterCoalescing::unsetRegisterKill(MachineInstr *MI, unsigned Reg) { for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { MachineOperand &MO = MI->getOperand(i); - if (MO.isReg() && MO.isKill() && MO.getReg() && + if (MO.isRegister() && MO.isKill() && MO.getReg() && mri_->regsOverlap(rep(MO.getReg()), Reg)) MO.unsetIsKill(); } @@ -1041,7 +1041,7 @@ for (unsigned i = 0, NumOps = MI->getNumOperands(); i != NumOps; ++i) { MachineOperand &MO = MI->getOperand(i); - if (MO.isReg() && MO.isKill() && MO.getReg() && + if (MO.isRegister() && MO.isKill() && MO.getReg() && mri_->regsOverlap(rep(MO.getReg()), Reg)) { MO.unsetIsKill(); } @@ -1056,7 +1056,7 @@ bool SimpleRegisterCoalescing::hasRegisterDef(MachineInstr *MI, unsigned Reg) { for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { MachineOperand &MO = MI->getOperand(i); - if (MO.isReg() && MO.isDef() && + if (MO.isRegister() && MO.isDef() && mri_->regsOverlap(rep(MO.getReg()), Reg)) return true; } Modified: llvm/trunk/lib/CodeGen/VirtRegMap.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/VirtRegMap.cpp?rev=41958&r1=41957&r2=41958&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/VirtRegMap.cpp (original) +++ llvm/trunk/lib/CodeGen/VirtRegMap.cpp Fri Sep 14 15:33:02 2007 @@ -446,7 +446,7 @@ SmallVector<unsigned, 1> *KillRegs = NULL) { for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { MachineOperand &MO = MI.getOperand(i); - if (!MO.isReg() || !MO.isUse() || !MO.isKill()) + if (!MO.isRegister() || !MO.isUse() || !MO.isKill()) continue; unsigned Reg = MO.getReg(); if (KillRegs) @@ -471,7 +471,7 @@ MachineOperand *DefOp = NULL; for (unsigned i = 0, e = DefMI->getNumOperands(); i != e; ++i) { MachineOperand &MO = DefMI->getOperand(i); - if (MO.isReg() && MO.isDef()) { + if (MO.isRegister() && MO.isDef()) { if (MO.getReg() == Reg) DefOp = &MO; else if (!MO.isDead()) @@ -488,7 +488,7 @@ MachineInstr *NMI = I; for (unsigned j = 0, ee = NMI->getNumOperands(); j != ee; ++j) { MachineOperand &MO = NMI->getOperand(j); - if (!MO.isReg() || MO.getReg() != Reg) + if (!MO.isRegister() || MO.getReg() != Reg) continue; if (MO.isUse()) FoundUse = true; @@ -511,7 +511,7 @@ const TargetInstrDescriptor *TID = MI.getInstrDescriptor(); for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { MachineOperand &MO = MI.getOperand(i); - if (!MO.isReg() || !MO.isUse()) + if (!MO.isRegister() || !MO.isUse()) continue; unsigned Reg = MO.getReg(); if (Reg == 0) @@ -535,7 +535,7 @@ for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { const MachineOperand &MO = MI.getOperand(i); - if (!MO.isReg() || !MO.isDef()) + if (!MO.isRegister() || !MO.isDef()) continue; unsigned Reg = MO.getReg(); RegKills.reset(Reg); @@ -826,7 +826,7 @@ bool CanReuse = true; int ti = TID->getOperandConstraint(i, TOI::TIED_TO); if (ti != -1 && - MI.getOperand(ti).isReg() && + MI.getOperand(ti).isRegister() && MI.getOperand(ti).getReg() == VirtReg) { // Okay, we have a two address operand. We can reuse this physreg as // long as we are allowed to clobber the value and there isn't an Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp?rev=41958&r1=41957&r2=41958&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp Fri Sep 14 15:33:02 2007 @@ -68,7 +68,7 @@ default: break; case ARM::LDR: if (MI->getOperand(1).isFrameIndex() && - MI->getOperand(2).isReg() && + MI->getOperand(2).isRegister() && MI->getOperand(3).isImmediate() && MI->getOperand(2).getReg() == 0 && MI->getOperand(3).getImmedValue() == 0) { @@ -102,7 +102,7 @@ default: break; case ARM::STR: if (MI->getOperand(1).isFrameIndex() && - MI->getOperand(2).isReg() && + MI->getOperand(2).isRegister() && MI->getOperand(3).isImmediate() && MI->getOperand(2).getReg() == 0 && MI->getOperand(3).getImmedValue() == 0) { @@ -521,7 +521,7 @@ bool Found = false; for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { const MachineOperand &MO = MI->getOperand(i); - if (MO.isReg() && MO.getReg() == ARM::CPSR) { + if (MO.isRegister() && MO.getReg() == ARM::CPSR) { Pred.push_back(MO); Found = true; } Modified: llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp?rev=41958&r1=41957&r2=41958&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp Fri Sep 14 15:33:02 2007 @@ -450,7 +450,7 @@ case 'I': // Write 'i' if an integer constant, otherwise nothing. Used to print // addi vs add, etc. - if (MI->getOperand(OpNo).isImm()) + if (MI->getOperand(OpNo).isImmediate()) O << "i"; return false; } Modified: llvm/trunk/lib/Target/PowerPC/PPCBranchSelector.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCBranchSelector.cpp?rev=41958&r1=41957&r2=41958&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCBranchSelector.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCBranchSelector.cpp Fri Sep 14 15:33:02 2007 @@ -129,7 +129,7 @@ unsigned MBBStartOffset = 0; for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I) { - if (I->getOpcode() != PPC::BCC || I->getOperand(2).isImm()) { + if (I->getOpcode() != PPC::BCC || I->getOperand(2).isImmediate()) { MBBStartOffset += getNumBytesForInstruction(I); continue; } Modified: llvm/trunk/lib/Target/TargetInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetInstrInfo.cpp?rev=41958&r1=41957&r2=41958&view=diff ============================================================================== --- llvm/trunk/lib/Target/TargetInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/TargetInstrInfo.cpp Fri Sep 14 15:33:02 2007 @@ -68,13 +68,13 @@ for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) { if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND)) { MachineOperand &MO = MI->getOperand(i); - if (MO.isReg()) { + if (MO.isRegister()) { MO.setReg(Pred[j].getReg()); MadeChange = true; - } else if (MO.isImm()) { + } else if (MO.isImmediate()) { MO.setImm(Pred[j].getImmedValue()); MadeChange = true; - } else if (MO.isMBB()) { + } else if (MO.isMachineBasicBlock()) { MO.setMachineBasicBlock(Pred[j].getMachineBasicBlock()); MadeChange = true; } Modified: llvm/trunk/lib/Target/X86/X86ATTAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ATTAsmPrinter.cpp?rev=41958&r1=41957&r2=41958&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ATTAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ATTAsmPrinter.cpp Fri Sep 14 15:33:02 2007 @@ -547,7 +547,7 @@ case 'h': // Print QImode high register case 'w': // Print HImode register case 'k': // Print SImode register - if (MI->getOperand(OpNo).isReg()) + if (MI->getOperand(OpNo).isRegister()) return printAsmMRegister(MI->getOperand(OpNo), ExtraCode[0]); printOperand(MI, OpNo); return false; Modified: llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp?rev=41958&r1=41957&r2=41958&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp (original) +++ llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp Fri Sep 14 15:33:02 2007 @@ -220,7 +220,7 @@ SmallVector<unsigned, 8> DeadRegs; for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { const MachineOperand &MO = MI->getOperand(i); - if (MO.isReg() && MO.isDead()) + if (MO.isRegister() && MO.isDead()) DeadRegs.push_back(MO.getReg()); } Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=41958&r1=41957&r2=41958&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Fri Sep 14 15:33:02 2007 @@ -291,9 +291,9 @@ static const MachineInstrBuilder &FuseInstrAddOperand(MachineInstrBuilder &MIB, MachineOperand &MO) { - if (MO.isReg()) + if (MO.isRegister()) MIB = MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit()); - else if (MO.isImm()) + else if (MO.isImmediate()) MIB = MIB.addImm(MO.getImm()); else if (MO.isFrameIndex()) MIB = MIB.addFrameIndex(MO.getFrameIndex()); @@ -340,7 +340,7 @@ for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { MachineOperand &MO = MI->getOperand(i); if (i == OpNo) { - assert(MO.isReg() && "Expected to fold into reg operand!"); + assert(MO.isRegister() && "Expected to fold into reg operand!"); unsigned NumAddrOps = MOs.size(); for (unsigned i = 0; i != NumAddrOps; ++i) MIB = FuseInstrAddOperand(MIB, MOs[i]); @@ -440,8 +440,8 @@ // instruction is different than folding it other places. It requires // replacing the *two* registers with the memory location. if (isTwoAddr && NumOps >= 2 && i < 2 && - MI->getOperand(0).isReg() && - MI->getOperand(1).isReg() && + MI->getOperand(0).isRegister() && + MI->getOperand(1).isRegister() && MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) { static const TableEntry OpcodeTable[] = { { X86::ADC32ri, X86::ADC32mi }, @@ -1528,7 +1528,7 @@ if (RetOpcode == X86::EH_RETURN) { MBBI = prior(MBB.end()); MachineOperand &DestAddr = MBBI->getOperand(0); - assert(DestAddr.isReg() && "Offset should be in register!"); + assert(DestAddr.isRegister() && "Offset should be in register!"); BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),StackPtr). addReg(DestAddr.getReg()); } _______________________________________________ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits