Author: djg Date: Mon Sep 17 09:55:08 2007 New Revision: 42027 URL: http://llvm.org/viewvc/llvm-project?rev=42027&view=rev Log: Use xorl instead of xorq to enter a zero into a 64-bit register.
Modified: llvm/trunk/lib/Target/X86/X86InstrX86-64.td Modified: llvm/trunk/lib/Target/X86/X86InstrX86-64.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrX86-64.td?rev=42027&r1=42026&r2=42027&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrX86-64.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrX86-64.td Mon Sep 17 09:55:08 2007 @@ -1018,13 +1018,15 @@ [(set GR64:$dst, (zextloadi64i32 addr:$src))]>; -// Alias instructions that map movr0 to xor. +// Alias instructions that map movr0 to xor. Use xorl instead of xorq; it's +// equivalent due to implicit zero-extending, and it sometimes has a smaller +// encoding. // FIXME: remove when we can teach regalloc that xor reg, reg is ok. // FIXME: AddedComplexity gives MOV64r0 a higher priority than MOV64ri32. Remove // when we have a better way to specify isel priority. let Defs = [EFLAGS], AddedComplexity = 1, isReMaterializable = 1 in def MOV64r0 : RI<0x31, MRMInitReg, (outs GR64:$dst), (ins), - "xor{q}\t$dst, $dst", + "xor{l}\t${dst:subreg32}, ${dst:subreg32}", [(set GR64:$dst, 0)]>; // Materialize i64 constant where top 32-bits are zero. _______________________________________________ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits