Author: djg
Date: Fri Oct 5 09:11:58 2007
New Revision: 42635
URL: http://llvm.org/viewvc/llvm-project?rev=42635&view=rev
Log:
Fix a typo in a comment.
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=42635&r1=42634&r2=42635&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Fri Oct 5
09:11:58 2007
@@ -1301,7 +1301,7 @@
I != E; ++I) {
if (I->isCtrl) continue;
SUnit *SuccSU = I->Dep;
- // Don't constraint nodes with implicit defs. It can create cycles
+ // Don't constrain nodes with implicit defs. It can create cycles
// plus it may increase register pressures.
if (SuccSU == SU || SuccSU->hasPhysRegDefs)
continue;
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