Author: djg Date: Thu Oct 11 18:21:31 2007 New Revision: 42881 URL: http://llvm.org/viewvc/llvm-project?rev=42881&view=rev Log: Set ISD::FPOW to Expand.
Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=42881&r1=42880&r2=42881&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Thu Oct 11 18:21:31 2007 @@ -240,7 +240,7 @@ setOperationAction(ISD::ConstantFP, MVT::f64, Expand); setOperationAction(ISD::ConstantFP, MVT::f32, Expand); - // We don't support sin/cos/fmod/copysign + // We don't support sin/cos/fmod/copysign/pow setOperationAction(ISD::FSIN , MVT::f64, Expand); setOperationAction(ISD::FSIN , MVT::f32, Expand); setOperationAction(ISD::FCOS , MVT::f32, Expand); @@ -249,6 +249,8 @@ setOperationAction(ISD::FREM , MVT::f32, Expand); setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); + setOperationAction(ISD::FPOW , MVT::f64, Expand); + setOperationAction(ISD::FPOW , MVT::f32, Expand); // int <-> fp are custom expanded into bit_convert + ARMISD ops. setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); Modified: llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp?rev=42881&r1=42880&r2=42881&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp Thu Oct 11 18:21:31 2007 @@ -93,7 +93,7 @@ setOperationAction(ISD::MEMSET , MVT::Other, Expand); setOperationAction(ISD::MEMCPY , MVT::Other, Expand); - // We don't support sin/cos/sqrt + // We don't support sin/cos/sqrt/pow setOperationAction(ISD::FSIN , MVT::f64, Expand); setOperationAction(ISD::FCOS , MVT::f64, Expand); setOperationAction(ISD::FSIN , MVT::f32, Expand); @@ -101,6 +101,9 @@ setOperationAction(ISD::FSQRT, MVT::f64, Expand); setOperationAction(ISD::FSQRT, MVT::f32, Expand); + + setOperationAction(ISD::FPOW , MVT::f32, Expand); + setOperationAction(ISD::FPOW , MVT::f64, Expand); setOperationAction(ISD::SETCC, MVT::f32, Promote); Modified: llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp?rev=42881&r1=42880&r2=42881&view=diff ============================================================================== --- llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp Thu Oct 11 18:21:31 2007 @@ -73,13 +73,15 @@ setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote); setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote); - // We don't support sin/cos/sqrt + // We don't support sin/cos/sqrt/pow setOperationAction(ISD::FSIN , MVT::f64, Expand); setOperationAction(ISD::FCOS , MVT::f64, Expand); setOperationAction(ISD::FSQRT, MVT::f64, Expand); + setOperationAction(ISD::FPOW , MVT::f64, Expand); setOperationAction(ISD::FSIN , MVT::f32, Expand); setOperationAction(ISD::FCOS , MVT::f32, Expand); setOperationAction(ISD::FSQRT, MVT::f32, Expand); + setOperationAction(ISD::FPOW , MVT::f32, Expand); // FIXME: IA64 supports fcopysign natively! setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=42881&r1=42880&r2=42881&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Thu Oct 11 18:21:31 2007 @@ -101,13 +101,15 @@ setOperationAction(ISD::UDIVREM, MVT::i64, Expand); setOperationAction(ISD::SDIVREM, MVT::i64, Expand); - // We don't support sin/cos/sqrt/fmod + // We don't support sin/cos/sqrt/fmod/pow setOperationAction(ISD::FSIN , MVT::f64, Expand); setOperationAction(ISD::FCOS , MVT::f64, Expand); setOperationAction(ISD::FREM , MVT::f64, Expand); + setOperationAction(ISD::FPOW , MVT::f64, Expand); setOperationAction(ISD::FSIN , MVT::f32, Expand); setOperationAction(ISD::FCOS , MVT::f32, Expand); setOperationAction(ISD::FREM , MVT::f32, Expand); + setOperationAction(ISD::FPOW , MVT::f32, Expand); // If we're enabling GP optimizations, use hardware square root if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) { Modified: llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp?rev=42881&r1=42880&r2=42881&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp Thu Oct 11 18:21:31 2007 @@ -205,6 +205,8 @@ setOperationAction(ISD::BSWAP, MVT::i32, Expand); setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); + setOperationAction(ISD::FPOW , MVT::f64, Expand); + setOperationAction(ISD::FPOW , MVT::f32, Expand); setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=42881&r1=42880&r2=42881&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu Oct 11 18:21:31 2007 @@ -440,6 +440,11 @@ setOperationAction(ISD::FCOS , MVT::f80 , Expand); } + // Always use a library call for pow. + setOperationAction(ISD::FPOW , MVT::f32 , Expand); + setOperationAction(ISD::FPOW , MVT::f64 , Expand); + setOperationAction(ISD::FPOW , MVT::f80 , Expand); + // First set operation action for all vector types to expand. Then we // will selectively turn on ones that can be effectively codegen'd. for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; @@ -471,6 +476,7 @@ setOperationAction(ISD::UMUL_LOHI, (MVT::ValueType)VT, Expand); setOperationAction(ISD::SDIVREM, (MVT::ValueType)VT, Expand); setOperationAction(ISD::UDIVREM, (MVT::ValueType)VT, Expand); + setOperationAction(ISD::FPOW, (MVT::ValueType)VT, Expand); } if (Subtarget->hasMMX()) { _______________________________________________ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits