Author: resistor Date: Mon Nov 12 01:39:39 2007 New Revision: 44012 URL: http://llvm.org/viewvc/llvm-project?rev=44012&view=rev Log: Add a flag for indirect branch instructions.
Target maintainers: please check that the instructions for your target are correctly marked. Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.td llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td llvm/trunk/lib/Target/Target.td llvm/trunk/lib/Target/X86/X86InstrInfo.td llvm/trunk/lib/Target/X86/X86InstrX86-64.td llvm/trunk/utils/TableGen/CodeGenInstruction.h llvm/trunk/utils/TableGen/CodeGenTarget.cpp llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrInfo.h?rev=44012&r1=44011&r2=44012&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetInstrInfo.h (original) +++ llvm/trunk/include/llvm/Target/TargetInstrInfo.h Mon Nov 12 01:39:39 2007 @@ -48,6 +48,7 @@ const unsigned M_DELAY_SLOT_FLAG = 1 << 4; const unsigned M_LOAD_FLAG = 1 << 5; const unsigned M_STORE_FLAG = 1 << 6; +const unsigned M_INDIRECT_FLAG = 1 << 7; // M_CONVERTIBLE_TO_3_ADDR - This is a 2-address instruction which can be // changed into a 3-address instruction if the first two operands cannot be @@ -237,6 +238,10 @@ return get(Opcode).Flags & M_BRANCH_FLAG; } + bool isIndirectBranch(MachineOpCode Opcode) const { + return get(Opcode).Flags & M_INDIRECT_FLAG; + } + /// isBarrier - Returns true if the specified instruction stops control flow /// from executing the instruction immediately following it. Examples include /// unconditional branches and return instructions. Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=44012&r1=44011&r2=44012&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Mon Nov 12 01:39:39 2007 @@ -773,7 +773,7 @@ def B : AXI<0xA, (outs), (ins brtarget:$target), Branch, "b $target", [(br bb:$target)]>; - let isNotDuplicable = 1 in { + let isNotDuplicable = 1, isIndirectBranch = 1 in { def BR_JTr : JTI<0x0, (outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id), "mov pc, $target \n$jt", [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>; Modified: llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.td?rev=44012&r1=44011&r2=44012&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.td (original) +++ llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.td Mon Nov 12 01:39:39 2007 @@ -374,8 +374,7 @@ def RETDAGp : MbrpForm< 0x1A, 0x02, (ops), "ret $$31,($$26),1", [(retflag)], s_jsr>; //Return from subroutine } -let isBranch = 1, isTerminator = 1, isBarrier = 1, -Ra = 31, disp = 0 in +let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1, Ra = 31, disp = 0 in def JMP : MbrpForm< 0x1A, 0x00, (ops GPRC:$RS), "jmp $$31,($RS),0", [(brind GPRC:$RS)], s_jsr>; //Jump Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td?rev=44012&r1=44011&r2=44012&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td (original) +++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td Mon Nov 12 01:39:39 2007 @@ -369,7 +369,8 @@ def BLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$p), "b${p:cc}lr ${p:reg}", BrB, [(retflag)]>; - def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>; + let isBranch = 1, isIndirectBranch = 1 in + def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>; } Modified: llvm/trunk/lib/Target/Target.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Target.td?rev=44012&r1=44011&r2=44012&view=diff ============================================================================== --- llvm/trunk/lib/Target/Target.td (original) +++ llvm/trunk/lib/Target/Target.td Mon Nov 12 01:39:39 2007 @@ -187,6 +187,7 @@ // instruction. bit isReturn = 0; // Is this instruction a return instruction? bit isBranch = 0; // Is this instruction a branch instruction? + bit isIndirectBranch = 0; // Is this instruction an indirect branch? bit isBarrier = 0; // Can control flow fall through this instruction? bit isCall = 0; // Is this instruction a call instruction? bit isLoad = 0; // Is this instruction a load instruction? Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=44012&r1=44011&r2=44012&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Mon Nov 12 01:39:39 2007 @@ -294,11 +294,11 @@ class IBr<bits<8> opcode, dag ins, string asm, list<dag> pattern> : I<opcode, RawFrm, (outs), ins, asm, pattern>; -// Indirect branches let isBranch = 1, isBarrier = 1 in def JMP : IBr<0xE9, (ins brtarget:$dst), "jmp\t$dst", [(br bb:$dst)]>; -let isBranch = 1, isTerminator = 1, isBarrier = 1 in { +// Indirect branches +let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst", [(brind GR32:$dst)]>; def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst", Modified: llvm/trunk/lib/Target/X86/X86InstrX86-64.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrX86-64.td?rev=44012&r1=44011&r2=44012&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrX86-64.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrX86-64.td Mon Nov 12 01:39:39 2007 @@ -120,7 +120,7 @@ []>; // Branches -let isBranch = 1, isTerminator = 1, isBarrier = 1 in { +let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { def JMP64r : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst", [(brind GR64:$dst)]>; def JMP64m : I<0xFF, MRM4m, (outs), (ins i64mem:$dst), "jmp{q}\t{*}$dst", Modified: llvm/trunk/utils/TableGen/CodeGenInstruction.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenInstruction.h?rev=44012&r1=44011&r2=44012&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenInstruction.h (original) +++ llvm/trunk/utils/TableGen/CodeGenInstruction.h Mon Nov 12 01:39:39 2007 @@ -87,6 +87,7 @@ // Various boolean values we track for the instruction. bool isReturn; bool isBranch; + bool isIndirectBranch; bool isBarrier; bool isCall; bool isLoad; Modified: llvm/trunk/utils/TableGen/CodeGenTarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenTarget.cpp?rev=44012&r1=44011&r2=44012&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenTarget.cpp (original) +++ llvm/trunk/utils/TableGen/CodeGenTarget.cpp Mon Nov 12 01:39:39 2007 @@ -379,6 +379,7 @@ isReturn = R->getValueAsBit("isReturn"); isBranch = R->getValueAsBit("isBranch"); + isIndirectBranch = R->getValueAsBit("isIndirectBranch"); isBarrier = R->getValueAsBit("isBarrier"); isCall = R->getValueAsBit("isCall"); isLoad = R->getValueAsBit("isLoad"); Modified: llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp?rev=44012&r1=44011&r2=44012&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp Mon Nov 12 01:39:39 2007 @@ -237,6 +237,7 @@ // Emit all of the target indepedent flags... if (Inst.isReturn) OS << "|M_RET_FLAG"; if (Inst.isBranch) OS << "|M_BRANCH_FLAG"; + if (Inst.isIndirectBranch) OS << "|M_INDIRECT_FLAG"; if (Inst.isBarrier) OS << "|M_BARRIER_FLAG"; if (Inst.hasDelaySlot) OS << "|M_DELAY_SLOT_FLAG"; if (Inst.isCall) OS << "|M_CALL_FLAG"; _______________________________________________ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits