Author: djg Date: Mon Nov 19 09:15:03 2007 New Revision: 44233 URL: http://llvm.org/viewvc/llvm-project?rev=44233&view=rev Log: Add support in SplitVectorOp for remainder operators.
Added: llvm/trunk/test/CodeGen/X86/split-vector-rem.ll Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=44233&r1=44232&r2=44233&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon Nov 19 09:15:03 2007 @@ -6341,7 +6341,10 @@ case ISD::FPOW: case ISD::AND: case ISD::OR: - case ISD::XOR: { + case ISD::XOR: + case ISD::UREM: + case ISD::SREM: + case ISD::FREM: { SDOperand LL, LH, RL, RH; SplitVectorOp(Node->getOperand(0), LL, LH); SplitVectorOp(Node->getOperand(1), RL, RH); Added: llvm/trunk/test/CodeGen/X86/split-vector-rem.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/split-vector-rem.ll?rev=44233&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/split-vector-rem.ll (added) +++ llvm/trunk/test/CodeGen/X86/split-vector-rem.ll Mon Nov 19 09:15:03 2007 @@ -0,0 +1,15 @@ +; RUN: llvm-as < %s | llc -march=x86-64 | grep div | count 16 +; RUN: llvm-as < %s | llc -march=x86-64 | grep fmodf | count 8 + +define <8 x i32> @foo(<8 x i32> %t, <8 x i32> %u) { + %m = srem <8 x i32> %t, %u + ret <8 x i32> %m +} +define <8 x i32> @bar(<8 x i32> %t, <8 x i32> %u) { + %m = urem <8 x i32> %t, %u + ret <8 x i32> %m +} +define <8 x float> @qux(<8 x float> %t, <8 x float> %u) { + %m = frem <8 x float> %t, %u + ret <8 x float> %m +} _______________________________________________ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits