Author: evancheng Date: Wed Jan 30 13:35:32 2008 New Revision: 46568 URL: http://llvm.org/viewvc/llvm-project?rev=46568&view=rev Log: A semi-gross fix for a debug info issue. When inserting the "function start" label (i.e. first label in the entry block) take care to insert it at the beginning of the block.
Modified: llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp Modified: llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h?rev=46568&r1=46567&r2=46568&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h (original) +++ llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h Wed Jan 30 13:35:32 2008 @@ -24,6 +24,7 @@ struct InstrStage; struct SUnit; class MachineConstantPool; + class MachineFunction; class MachineModuleInfo; class MachineRegisterInfo; class MachineInstr; @@ -243,6 +244,7 @@ const TargetMachine &TM; // Target processor const TargetInstrInfo *TII; // Target instruction information const MRegisterInfo *MRI; // Target processor register info + MachineFunction *MF; // Machine function MachineRegisterInfo &RegInfo; // Virtual/real register map MachineConstantPool *ConstPool; // Target constant pool std::vector<SUnit*> Sequence; // The schedule. Null SUnit*'s Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp?rev=46568&r1=46567&r2=46568&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp Wed Jan 30 13:35:32 2008 @@ -31,6 +31,7 @@ const TargetMachine &tm) : DAG(dag), BB(bb), TM(tm), RegInfo(BB->getParent()->getRegInfo()) { TII = TM.getInstrInfo(); + MF = &DAG.getMachineFunction(); MRI = TM.getRegisterInfo(); ConstPool = BB->getParent()->getConstantPool(); } @@ -710,13 +711,30 @@ } // Now that we have emitted all operands, emit this instruction itself. - if (!II.usesCustomDAGSchedInsertionHook()) { - BB->insert(BB->end(), MI); - } else { - // Insert this instruction into the end of the basic block, potentially - // taking some custom action. + if (Opc == TargetInstrInfo::LABEL && + !BB->empty() && &MF->front() == BB) { + // If we are inserting a LABEL and this happens to be the first label in + // the entry block, it is the "function start" label. Make sure there are + // no other instructions before it. + bool SeenLabel = false; + MachineBasicBlock::iterator MBBI = BB->begin(); + while (MBBI != BB->end()) { + if (MBBI->getOpcode() == TargetInstrInfo::LABEL) { + SeenLabel = true; + break; + } + ++MBBI; + } + if (!SeenLabel) + BB->insert(BB->begin(), MI); + else + BB->push_back(MI); + } else if (II.usesCustomDAGSchedInsertionHook()) + // Insert this instruction into the basic block using a target + // specific inserter which may returns a new basic block. BB = DAG.getTargetLoweringInfo().EmitInstrWithCustomInserter(MI, BB); - } + else + BB->push_back(MI); // Additional results must be an physical register def. if (HasPhysRegOuts) { @@ -870,13 +888,12 @@ // If this is the first basic block in the function, and if it has live ins // that need to be copied into vregs, emit the copies into the top of the // block before emitting the code for the block. - MachineFunction &MF = DAG.getMachineFunction(); - if (&MF.front() == BB) { + if (&MF->front() == BB) { for (MachineRegisterInfo::livein_iterator LI = RegInfo.livein_begin(), E = RegInfo.livein_end(); LI != E; ++LI) if (LI->second) { const TargetRegisterClass *RC = RegInfo.getRegClass(LI->second); - TII->copyRegToReg(*MF.begin(), MF.begin()->end(), LI->second, + TII->copyRegToReg(*MF->begin(), MF->begin()->end(), LI->second, LI->first, RC, RC); } } _______________________________________________ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits