Author: sampo Date: Tue Feb 12 20:58:33 2008 New Revision: 47045 URL: http://llvm.org/viewvc/llvm-project?rev=47045&view=rev Log: Make register scavenging happy by not using a reg (CR0) that isn't defined
Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td?rev=47045&r1=47044&r2=47045&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td (original) +++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td Tue Feb 12 20:58:33 2008 @@ -293,7 +293,7 @@ // PowerPC Predicate operand. 20 = (0<<5)|20 = always, CR0 is a dummy reg // that doesn't matter. def pred : PredicateOperand<OtherVT, (ops imm, CRRC), - (ops (i32 20), CR0)> { + (ops (i32 20), (i32 zero_reg))> { let PrintMethod = "printPredicateOperand"; } _______________________________________________ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits