http://llvm.org/bugs/show_bug.cgi?id=4682
Summary: Invalid assembler emitted for some thumb instructions
Product: libraries
Version: trunk
Platform: PC
OS/Version: Linux
Status: NEW
Severity: normal
Priority: P2
Component: Backend: ARM
AssignedTo: [email protected]
ReportedBy: [email protected]
CC: [email protected]
Created an attachment (id=3284)
--> (http://llvm.org/bugs/attachment.cgi?id=3284)
picadd.bc
Consider the attached 2 testcases
1. Reproduce with llc picadd.bc -relocation-model=pic
Invalid "add.w r0, r0, pc" instruction is emitted. It has 3 register operands
and 'w' suffix thus it's treated as T3 instruction by assembler (no other
variant is possible due to 'w' suffix - assembler *must* use wide variant).
However It's not possible to use sp and pc registers as dest and rhs registers
for this encoding.
It's really should be T1 or T2 instruction (and thus - narrow) with dst = lhs.
2. Reproduce with llc subsp.bc
Invalid "sub.w sp, r7, #8" instruction is emitted.
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