http://llvm.org/bugs/show_bug.cgi?id=6722
Summary: [ARM] Model VLD/VST latencies properly
Product: libraries
Version: trunk
Platform: PC
OS/Version: All
Status: NEW
Severity: normal
Priority: P
Component: Common Code Generator Code
AssignedTo: [email protected]
ReportedBy: [email protected]
CC: [email protected]
VLD / VST instructions have different latencies depending on amount of register
they write, how, etc. We need to model these latencies properly.
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