http://llvm.org/bugs/show_bug.cgi?id=8958
Summary: Hit assertion in SelectionDAG.cpp for the attached
code
Product: libraries
Version: trunk
Platform: PC
OS/Version: Linux
Status: NEW
Severity: normal
Priority: P
Component: Backend: X86
AssignedTo: [email protected]
ReportedBy: [email protected]
CC: [email protected]
Assertion failed: !VT.isVector() && "getZeroExtendInReg should use the vector
element type instead of " "the vector type!", file
..\..\..\..\..\llvm\lib\CodeGen\SelectionDAG\SelectionDAG.cpp, line 855
Checked on today's trunk.
; ModuleID = 'bugpoint-reduced-simplified.bc'
target datalayout =
"e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f80:128:128-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32"
target triple = "i686-pc-win32"
define void @m_387() nounwind {
%1 = load <4 x i8> addrspace(1)* undef, align 1
%2 = zext <4 x i8> %1 to <4 x i32>
store <4 x i32> %2, <4 x i32> addrspace(1)* undef, align 4
ret void
}
Fix forthcoming.
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