http://llvm.org/bugs/show_bug.cgi?id=9139
Summary: CodeGen/ARM/vector-DAGCombine.ll fails
Product: libraries
Version: trunk
Platform: Other
OS/Version: Linux
Status: NEW
Severity: normal
Priority: P
Component: Backend: ARM
AssignedTo: [email protected]
ReportedBy: [email protected]
CC: [email protected], [email protected]
This test fails on a beagleboard:
define void @i64_buildvector(i64* %ptr, <2 x i64>* %vp) nounwind {
; CHECK: i64_buildvector
; CHECK: vldr.64
%t0 = load i64* %ptr, align 4
%t1 = insertelement <2 x i64> undef, i64 %t0, i32 0
store <2 x i64> %t1, <2 x i64>* %vp
ret void
}
The produced assembly reads:
.globl i64_buildvector
.align 2
.type i64_buildvector,%function
i64_buildvector: @ @i64_buildvector
@ BB#0:
ldr r2, [r0]
ldr r0, [r0, #4]
vmov d16, r2, r0
vstmia r1, {d16, d17}
mov pc, lr
.Ltmp5:
.size i64_buildvector, .Ltmp5-i64_buildvector
On my x86-64 box I get:
@ BB#0:
vldr.64 d16, [r0]
vstmia r1, {d16, d17}
mov pc, lr
which matches the test. Do we need a full target triple to make this happen?
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