http://llvm.org/bugs/show_bug.cgi?id=9538
Summary: Verifier accepts non-sensical intrinsics involving
vectors
Product: new-bugs
Version: unspecified
Platform: PC
OS/Version: Linux
Status: NEW
Severity: normal
Priority: P
Component: new bugs
AssignedTo: [email protected]
ReportedBy: [email protected]
CC: [email protected]
Testcase:
declare {<4 x i32>, i1} @llvm.umul.with.overflow.v4i32(<4 x i32> %a, <4 x i32>
%b)
define i1 @a(<4 x i32> %x) {
%r = call {<4 x i32>, i1} @llvm.umul.with.overflow.v4i32(<4 x i32> %x, <4 x
i32> %x)
%s = extractvalue {<4 x i32>, i1} %r, 1
ret i1 %s
}
This clearly doesn't make any sense, but the verifier accepts it. Perhaps the
definitions of some intrinsics need to be tightened up a bit?
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