http://llvm.org/bugs/show_bug.cgi?id=9947
Summary: Instruction selection places memory operands on the
wrong instructions
Product: libraries
Version: trunk
Platform: PC
OS/Version: All
Status: NEW
Severity: normal
Priority: P
Component: Common Code Generator Code
AssignedTo: [email protected]
ReportedBy: [email protected]
CC: [email protected]
It appears that for some patterns, isel puts the memory operands on the wrong
MachineInstructions. All of the remaining verifier failures in the "make check"
tests are due to this problem. Here is a simple example:
********************
FAIL: LLVM :: CodeGen/X86/break-sse-dep.ll (2322 of 6038)
******************** TEST 'LLVM :: CodeGen/X86/break-sse-dep.ll' FAILED
********************
Script:
--
/Volumes/Data/b/Release+Asserts/bin/llc <
/Volumes/Data/l/test/CodeGen/X86/break-sse-dep.ll -mtriple=x86_64-linux
-mattr=+sse2 | /Volumes/Data/b/Release+Asserts/bin/FileCheck
/Volumes/Data/l/test/CodeGen/X86/break-sse-dep.ll
/Volumes/Data/b/Release+Asserts/bin/llc <
/Volumes/Data/l/test/CodeGen/X86/break-sse-dep.ll -mtriple=x86_64-win32
-mattr=+sse2 | /Volumes/Data/b/Release+Asserts/bin/FileCheck
/Volumes/Data/l/test/CodeGen/X86/break-sse-dep.ll
--
Exit Code: 1
Command Output (stderr):
--
# Before register coalescing
# Machine code for function t1:
Function Live Ins: %RDI in %vreg0
Function Live Outs: %XMM0
0L BB#0: derived from LLVM BB %entry
Live Ins: %RDI
16L %vreg0<def> = COPY %RDI<kill>; GR64:%vreg0
32L %vreg1<def> = MOVSSrm %vreg0<kill>, 1, %noreg, 0, %noreg;
FR32:%vreg1 GR64:%vreg0
48L %vreg2<def> = CVTSS2SDrr %vreg1<kill>; mem:LD4[%x] FR64:%vreg2
FR32:%vreg1
64L %XMM0<def> = COPY %vreg2<kill>; FR64:%vreg2
80L RET %XMM0<imp-use,kill>
# End machine code for function t1.
*** Bad machine code: Missing mayLoad flag ***
- function: t1
- basic block: entry 0x7fc41b0337a0 (BB#0) [0L;96L)
- instruction: 48L %vreg2<def> = CVTSS2SDrr %vreg1<kill>; mem:LD4[%x]
FR64:%vreg2 FR32:%vreg1
LLVM ERROR: Found 1 machine code errors.
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