http://llvm.org/bugs/show_bug.cgi?id=10653
Summary: Vector INREG_SEXTEND is broken on ARM
Product: libraries
Version: trunk
Platform: All
OS/Version: All
Status: NEW
Severity: normal
Priority: P
Component: Backend: ARM
AssignedTo: [email protected]
ReportedBy: [email protected]
CC: [email protected]
In my work on vector-select I found a bug which is exposed when calling
PromoteIntOp_SIGN_EXTEND with vector types. In this code an SIGN_EXTEND_INREG
ISD node is created. Later, when we attempt to legalize the SIGN_EXTEND_INREG
ISD node, we generate vector SHL and SHR code (which is okay). The problem is
that the shift amount may be an illegal ARM type. For example, if we want to
perform an SIGN_EXTEND_INREG of v8i8 types (legal on arm), we would create a
vector (BUILD_VECTOR of i8 scalars). The i8 scalars are illegal.
I am not sure what the right fix is.
--
Configure bugmail: http://llvm.org/bugs/userprefs.cgi?tab=email
------- You are receiving this mail because: -------
You are on the CC list for the bug.
_______________________________________________
LLVMbugs mailing list
[email protected]
http://lists.cs.uiuc.edu/mailman/listinfo/llvmbugs
