http://llvm.org/bugs/show_bug.cgi?id=10855
Summary: llc miscompiles negation of long long (ARM)
Product: tools
Version: trunk
Platform: PC
OS/Version: All
Status: NEW
Severity: release blocker
Priority: P
Component: llc
AssignedTo: [email protected]
ReportedBy: [email protected]
CC: [email protected]
This bug started happening at revision 138791.
Compile this bitcode for ARM:
target triple = "armv7-none-linux-gnueabi"
define i64 @foo(i64 %x) nounwind readnone {
entry:
%0 = sub nsw i64 0, %x
ret i64 %0
}
The resulting code for foo is:
rsb r0, r0, #0
rsc r1, r1, #0
bx lr
The correct code is:
rsbs r0, r0, #0
rsc r1, r1, #0
bx lr
(rsc uses the carry bit provided by rsbs)
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