http://llvm.org/bugs/show_bug.cgi?id=11025
Summary: Represent hadd, vector shift without target specific
builtins.
Product: clang
Version: trunk
Platform: PC
OS/Version: All
Status: NEW
Severity: enhancement
Priority: P
Component: Headers
AssignedTo: [email protected]
ReportedBy: [email protected]
CC: [email protected]
We should try to reduce the amount of target specific builtins used to
implement intrinsics, if we can represent them with standard IR and the machine
code output is still the same. This makes the optimizer's job easier.
Eventually we can remove those builtins entirely (llvm-gcc will still generate
them so we need to autoupgrade).
===
Thanks to Duncan's recent work, the X86 backend can match horizontal add and
sub of fp vectors now, so we can represent it as shufflevectors + fadd.
static __inline__ __m128d __attribute__((__always_inline__, __nodebug__))
_mm_hadd_pd(__m128d a, __m128d b)
{
return __builtin_shufflevector(a, b, 0, 2) + __builtin_shufflevector(a, b, 1,
3);
}
similar for hsub_pd, hadd_ps and hsub_ps.
===
Vector shift support should also be solid enough now, so we can rewrite the
shift intrinsics:
static __inline__ __m128i __attribute__((__always_inline__, __nodebug__))
_mm_slli_epi16(__m128i a, int count)
{
return (__m128i)((__v8hi)a << (__v8hi){ count, count, count, count,
count, count, count, count });
}
We have to be careful here though, some x86 shift instructions don't support
variable shifts. Not sure if we want to allow it and emit unexpected code (or
crash the backend).
===
minsd/maxsd and friends should be representable with something like "return a <
b ? a : b" and let the backend do the heavy lifting, I couldn't come up with a
way to create the necessary vector compares in C code though.
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