http://llvm.org/bugs/show_bug.cgi?id=12519
Bug #: 12519
Summary: llc produce wrong assembly for ARM on following .ll
code
Product: new-bugs
Version: 3.0
Platform: PC
OS/Version: Linux
Status: NEW
Severity: enhancement
Priority: P
Component: new bugs
AssignedTo: [email protected]
ReportedBy: [email protected]
CC: [email protected]
Classification: Unclassified
Created attachment 8368
--> http://llvm.org/bugs/attachment.cgi?id=8368
ll file to reproduce problem
On attached .ll file when compiled with llc 3.0 as follows:
llc vabug.ll -march=arm -mcpu=cortex-a9 -mattr=+neon,+neonfp
-relocation-model=pic -o vabug.s
llc produce following ARM code:
...
ldr r0, [sp, #4]
add r1, r0, #4
str r1, [sp, #4]
ldrb r1, [r0], #11
and r0, r0, #248 # BUG HERE ?
add r2, r0, #16
str r1, [sp, #96]
str r2, [sp, #4]
vldr.64 d16, [r0]
mov r0, r4
vcvt.s32.f64 s0, d16
vstr.32 s0, [sp, #100]
bl check(PLT)
...
I think line marked as 'BUG HERE' is incorrect. I'm expecting llc to generate
instruction:
...
bfc r0, #0, #3
...
Correct code is generated when I change 'zext' by 'sext' in LLVM code line #31,
which to me doesn't make sense.
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