http://llvm.org/bugs/show_bug.cgi?id=14859
Bug #: 14859
Summary: Lost "memory" constraint in clobber list in inline asm
Product: libraries
Version: trunk
Platform: PC
OS/Version: Linux
Status: NEW
Severity: enhancement
Priority: P
Component: Common Code Generator Code
AssignedTo: [email protected]
ReportedBy: [email protected]
CC: [email protected]
Classification: Unclassified
The "memory" constraint in the clobber list in inline asm is translated by the
front-end to a string "{memory}" in the LLVM IR's representation of the inline
asm. During the translation of the IR into machine instructions, the constraint
string is not recognized properly, possibly resulting in generating invalid
code.
Consider, for example, the following code:
--- asm.c ---
int G;
int foo(char *p) {
int rv;
G = 0;
asm ("" : "=r"(rv)
: "r"(p)
: "memory");
return rv + G;
}
-------------
Immediately before generating the machine instructions, the function looks like
this:
*** IR Dump Before Module Verifier ***
define i32 @foo(i8* %p) nounwind uwtable {
entry:
store i32 0, i32* @G, align 4, !tbaa !0
%0 = tail call i32 asm "", "=r,r,~{memory},~{dirflag},~{fpsr},~{flags}"(i8*
%p) nounwind, !srcloc !3
%1 = load i32* @G, align 4, !tbaa !0
%add = add nsw i32 %1, %0
ret i32 %add
}
But after instruction selection, the memory clobbering constraint seems to be
lost (there is no load from G):
# *** IR Dump Before Expand ISel Pseudo-instructions ***:
# Machine code for function foo: SSA
Function Live Ins: %RDI in %vreg0
Function Live Outs: %EAX
BB#0: derived from LLVM BB %entry
Live Ins: %RDI
%vreg0<def> = COPY %RDI; GR64:%vreg0
MOV32mi %RIP, 1, %noreg, <ga:@G>, %noreg, 0; mem:ST4[@G](tbaa=!"int")
%vreg2<def> = COPY %vreg0; GR64:%vreg2,%vreg0
INLINEASM <es:> [attdialect], $0:[regdef:GR32], %vreg1<def>,
$1:[reguse:GR64], %vreg2, $2:[clobber], %EFLAGS<earlyclobber,imp-def>,
<<badref>>; GR32:%vreg1 GR64:%vreg2
%EAX<def> = COPY %vreg1; GR32:%vreg1
RET
# End machine code for function foo.
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