http://llvm.org/bugs/show_bug.cgi?id=14867
Bug #: 14867
Summary: ARM poor vector code generation zext 8xi8 to 8xi32
Product: libraries
Version: trunk
Platform: PC
OS/Version: All
Status: NEW
Severity: enhancement
Priority: P
Component: Backend: ARM
AssignedTo: [email protected]
ReportedBy: [email protected]
CC: [email protected]
Classification: Unclassified
The LL code below is compiled to a really long sequence of ARM instructions
(thumb/swift). There must be a better way to lower this code.
%T0_11 = type <8 x i8>
%T1_11 = type <8 x i32>
define void @func11() {
%v0 = load %T0_11* undef
%r = sext %T0_11 %v0 to %T1_11
store %T1_11 %r, %T1_11* undef
ret void
}
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