http://llvm.org/bugs/show_bug.cgi?id=15155
Bug #: 15155
Summary: PPC: Optimize vector splats with more than 3 bits
better.
Product: libraries
Version: trunk
Platform: PC
OS/Version: All
Status: NEW
Severity: enhancement
Priority: P
Component: Backend: PowerPC
AssignedTo: [email protected]
ReportedBy: [email protected]
CC: [email protected]
Classification: Unclassified
After r174325 we compile
define <4 x i32> @foo() {
ret <4 x i32> <i32 16, i32 16, i32 16, i32 16>
}
into a load:
ld 3, .LC1@toc(2)
lvx 2, 0, 3
blr
instead of a splat:
vspltisw 2, 8
vadduwm 2, 2, 2
blr
The code in PPCISelLowering.cpp that generates the splat was disabled in
r174325 because it fails to cope with constant folding of the ADD node.
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