http://llvm.org/bugs/show_bug.cgi?id=15247
Renato Golin <[email protected]> changed: What |Removed |Added ---------------------------------------------------------------------------- Status|NEW |RESOLVED Resolution|--- |INVALID --- Comment #5 from Renato Golin <[email protected]> --- I just remembered that the 64-bit floats are done in the VFP pipeline, so only access to double registers, thus only doing one 64-bit FP operation per cycle (at most). All instructions seem to be VFP, and also generated on the non-vectorized case. Debugging the loop vectorizer I just learnt that it's not vectorizing anything, the VFP instructions are comming from the fact that it's hard-fp and VFP.64 is faster than soft-fp math libraries. Silly me... -- You are receiving this mail because: You are on the CC list for the bug.
_______________________________________________ LLVMbugs mailing list [email protected] http://lists.cs.uiuc.edu/mailman/listinfo/llvmbugs
