http://llvm.org/bugs/show_bug.cgi?id=16429
Bug ID: 16429
Summary: Missed optimization in CMPXCHG-loop
Product: new-bugs
Version: trunk
Hardware: PC
OS: All
Status: NEW
Severity: enhancement
Priority: P
Component: new bugs
Assignee: [email protected]
Reporter: [email protected]
CC: [email protected]
Classification: Unclassified
Created attachment 10749
--> http://llvm.org/bugs/attachment.cgi?id=10749&action=edit
bitcode using atomicrmw and cmpxchg-loop
An atomicrmw with an operation different from "add" and "sub" gets translated
to a cmpxchg-loop on x86, since there is no single hardware instruction for
doing that.
If you try to write that loop manually however, the generated assembly is
longer and uses one more register.
The backend seems to miss the fact that cmpxchg does set the ZF flag, and hence
emits an unnecessary cmp.
I attached a bitcode file containing two methods. "bar" uses an atomicrmw
instruction, "baz" a cmpxchg-loop. "bar" results in optimal assembly, "baz"
contains an additional cmp plus several movs, and uses one more register.
I generate assembly using "llc -o - test.ll".
This is the non-optimal assembly part:
[...]
movl L_foo(%rip), %eax
LBB1_1: ## %loop
(1) movl %eax, %ecx
(2) movl %ecx, %edx
andl %edi, %edx
lock
cmpxchgl %edx, L_foo(%rip)
(3) cmpl %eax, %ecx
jne LBB1_1
[...]
Lines (2) and (3) can be skipped completely if (1) copies to %edx directly.
This also saves register %ecx. This would also match the code generated for the
atomicrmw instruction.
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