http://llvm.org/bugs/show_bug.cgi?id=17029
Bug ID: 17029
Summary: add support for AMD TBM instructions
Product: libraries
Version: trunk
Hardware: PC
OS: All
Status: NEW
Severity: normal
Priority: P
Component: Backend: X86
Assignee: [email protected]
Reporter: [email protected]
CC: [email protected]
Classification: Unclassified
An even more efficient codegen solution to bug 17028 is to use the "bextr"
instruction that takes an immediate rather than a register. This instruction is
available on AMD chips such as Bulldozer, ver2 that implement "TBM". However,
it doesn't appear that a "HasTBM" CPU feature is implemented in LLVM as of
r189409.
--
You are receiving this mail because:
You are on the CC list for the bug.
_______________________________________________
LLVMbugs mailing list
[email protected]
http://lists.cs.uiuc.edu/mailman/listinfo/llvmbugs
