http://llvm.org/bugs/show_bug.cgi?id=17485
Bug ID: 17485
Summary: llvm and gcc disagree on who supports x86 cmpxchg16b
Product: new-bugs
Version: unspecified
Hardware: PC
OS: Linux
Status: NEW
Severity: normal
Priority: P
Component: new bugs
Assignee: [email protected]
Reporter: [email protected]
CC: [email protected]
Classification: Unclassified
There are three architectures, k8-sse3 opteron-sse3 and athlon64-sse3 for which
gcc does not define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 , but llvm's X86.td
claims they do support the cmpxchg16b instruction. What's the cause of this
discrepancy?
We should either:
a) Remove CPUXCHG16B from the architectures in X86.td because the CPUs don't
support it. It's just an LLVM bug.
b) Add __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 in clang for those architectures
because they do support it. It's just a GCC bug.
c) Leave it as is, but add a comment explaining why. Does the CPU support it
but we need to not define the macro for GCC compatibility? Does the CPU support
it but with some horrible flaw?
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