http://llvm.org/bugs/show_bug.cgi?id=18014
Bug ID: 18014
Summary: llc handles "sext" instruction with constants
incorrect
Product: tools
Version: trunk
Hardware: PC
OS: Linux
Status: NEW
Severity: normal
Priority: P
Component: llc
Assignee: [email protected]
Reporter: [email protected]
CC: [email protected]
Classification: Unclassified
Created attachment 11580
--> http://llvm.org/bugs/attachment.cgi?id=11580&action=edit
Reproducer
Reproducer for this issue:
; ModuleID = 'bad.bc'
target datalayout =
"e-p:64:64:64-S128-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f16:16:16-f32:32:32-f64:64:64-f128:128:128-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
target triple = "x86_64-unknown-linux-gnu"
; Function Attrs: nounwind
define i32 @f_fu(<8 x i32>* %RET, <8 x i32>* %temp) #2 {
allocas:
%temp_1 = load <8 x i32>* %temp
%sext_val = sext <8 x i1> <i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1> to
<8 x i32>
%mask = and <8 x i32> %sext_val, %temp_1
%one_of_mask = extractelement <8 x i32> %mask, i32 3
%new_mask = insertelement <8 x i32> zeroinitializer, i32 %one_of_mask, i32 1
%blend = select <8 x i1> <i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1>, <8
x i32> %new_mask, <8 x i32> zeroinitializer
store <8 x i32> %blend, <8 x i32>* %RET
ret i32 %one_of_mask
}
attributes #2 = { nounwind "target-cpu"="corei7-avx"
"target-features"="+sse,+sse2,+sse3,-sse4a,+ssse3,-popcnt,+cmov,+sse4.1,-sse4.2"
}
to reproduce:
llc bad.ll -mcpu=westmere
clang++ -O2 -m64 test.cpp bad.s -o test.run
./test.run
(File test.cpp is attached)
Here we sext i1 array of ones to i32 array of ones. Then and them with input
array and return third element of the result.
We should have an answer 4 (because it is the value of third element of input
array). But we will have answer 0 and it is incorrect. Possible it happens due
to missing pslld and psrad instructions before "and" instruction in generated
asm.
If we comment last strings:
; %new_mask = insertelement <8 x i32> zeroinitializer, i32 %one_of_mask, i32 1
; %blend = select <8 x i1> <i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1>,
<8 x i32> %new_mask, <8 x i32> zeroinitializer
; store <8 x i32> %blend, <8 x i32>* %RET
We will have right answer and right shifts in generated asm.
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