http://llvm.org/bugs/show_bug.cgi?id=21478
Bug ID: 21478
Summary: MIPS assertions failed when disassembling SC and CACHE
instructions
Product: libraries
Version: trunk
Hardware: PC
OS: All
Status: NEW
Severity: normal
Priority: P
Component: Backend: MIPS
Assignee: [email protected]
Reporter: [email protected]
CC: [email protected]
Classification: Unclassified
A few instructions in the MIPS back end (SC and CACHE) have MemOpnd operands
that confuse the disassembler. They are a single operand, but the disassembler
treats them as two, resulting assertion failures because the operands are out
of range.
--
You are receiving this mail because:
You are on the CC list for the bug.
_______________________________________________
LLVMbugs mailing list
[email protected]
http://lists.cs.uiuc.edu/mailman/listinfo/llvmbugs
