http://llvm.org/bugs/show_bug.cgi?id=21790
Bug ID: 21790
Summary: wrong load instruction type generated for vector FP
add (x86)
Product: libraries
Version: trunk
Hardware: PC
OS: All
Status: NEW
Severity: normal
Priority: P
Component: Backend: X86
Assignee: [email protected]
Reporter: [email protected]
CC: [email protected]
Classification: Unclassified
In the following test case, we want to load the 2 lower floats in a v4f32 and
add them to some other v4f32:
$ cat wrong_load.ll
define <4 x float> @add_2_floats(float* nocapture %p, <4 x float> %x) {
%f1 = load float* %p
%vecins1 = insertelement <4 x float> undef, float %f1, i32 0
%add.ptr = getelementptr float* %p, i32 1
%f2 = load float* %add.ptr
%vecins2 = insertelement <4 x float> %vecins1, float %f2, i32 1
%y = fadd <4 x float> %vecins2, %x
ret <4 x float> %y
}
$ ./llc wrong_load.ll -o -
...
movq (%rdi), %xmm1 <--- integer load
addps %xmm1, %xmm0 <--- floating-point math op
retq
---------------------------------------------------------------------------
We're generating an i64 load instead of the FP instruction for loading 2
floats: 'movlps'. This may cause a domain-crossing penalty.
The bug is located in X86ISelLowering's "EltsFromConsecutiveLoads()" function.
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