http://llvm.org/bugs/show_bug.cgi?id=22662
Bug ID: 22662
Summary: Support relaxation of more x86 instructions
Product: libraries
Version: trunk
Hardware: PC
OS: Linux
Status: NEW
Severity: normal
Priority: P
Component: Backend: X86
Assignee: [email protected]
Reporter: [email protected]
CC: [email protected]
Classification: Unclassified
$ cat foo.S
.code16
movl (foo), %ebx
foo:
$ llvm-mc -filetype=obj foo.S | llvm-objdump -d -triple=i686-pc-linux-code16 -
<stdin>: file format ELF64-x86-64
Disassembly of section .text:
.text:
0: 67 66 8b 1d 00 00 00 00 movl 0, %ebx
We didn't need the 0x67 addr32 prefix for this. GCC does this:
0: 66 8b 1e 00 00 movl 0, %ebx
Although not strictly incorrect, this causes a problem for size-sensitive code;
the above example was taken from a boot sector implementation.
We should emit the 16-bit version by default. And if we do that, we're going to
need to handle relaxation for the case where it *isn't* sufficient.
We normally handle relaxation by converting to a *different* opcode. That isn't
sufficient here; we'll probably need a flag in the MCInst to indicate that it
should use addr32. Which is nice, since we already *wanted* to support the
explicit 'addr32' prefix...
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