https://llvm.org/bugs/show_bug.cgi?id=23085
Bug ID: 23085
Summary: [AArch64] Useless register shuffling with tail-call
Product: libraries
Version: trunk
Hardware: PC
OS: Linux
Status: NEW
Severity: normal
Priority: P
Component: Backend: AArch64
Assignee: [email protected]
Reporter: [email protected]
CC: [email protected], [email protected]
Classification: Unclassified
Created attachment 14124
--> https://llvm.org/bugs/attachment.cgi?id=14124&action=edit
testcase
For the attached testcase, LLVM produces:
clang --target aarch64 tail-call-allocation.c -O2 -S
foo:
mov w8, w0 /* Poor register choice. */
movz w9, #0x4e20
cmp w8, w9
b.le .LBB0_2
mov w0, w8
ret
.LBB0_2:
mov w0, wzr
add w1, w8, w8, lsl #6
b bar
GCC produces:
foo:
mov w2, 20000
cmp w0, w2
ble .L4
ret
.p2align 3
.L4:
add w1, w0, w0, lsl 6
mov w0, 0
b bar
In the LLVM case, the scheduling of:
mov w0, wzr
add w1, w8, w8, lsl #6
prevents better register allocation as the live range for w0 as an outgoing
argument overlaps with that of w0 as an incoming argument.
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