https://llvm.org/bugs/show_bug.cgi?id=23423
Bug ID: 23423
Summary: [TableGen] Register Pressure information is wrong for
x86
Product: tools
Version: trunk
Hardware: PC
OS: All
Status: NEW
Severity: normal
Priority: P
Component: TableGen
Assignee: [email protected]
Reporter: [email protected]
CC: [email protected]
Classification: Unclassified
While helping Daniel Jasper for http://reviews.llvm.org/D8998, which teach
MachineLICM how to deal with register masks to make it register pressure aware,
I found a bug in the tables that describe the register pressure.
The bug appears only when we have partially defined register aliasing patterns.
I.e., given a register class RC, some of the registers in RC do not have the
same number of register unit.
E.g., on X86, we have:
AX = AH AL
but
R8W = R8B
I am not exactly sure why it happens, but because of that difference, table gen
creates fake reg units that do not increase the number of available unit for
each register class, but that are not accessible. Therefore, we have less
available space than we actually think when doing the analysis.
E.g., the previous example becomes:
AX = AH AL
but
R8W = N/A R8B
Where N/A is not accessible. Now a regclass with both AX and R8W would give 4
as register limit instead of 3.
* STEPS TO REPRODUCE
<llvm_build>/Debug+Asserts/bin/llvm-tblgen -I <llvm_src>/lib/Target/X86 -I
<llvm_src>/include -I <llvm_src>/include -I <llvm_src>/lib/Target
-gen-register-info -o
<llvm_build>/lib/Target/X86/Debug+Asserts/X86GenRegisterInfo.inc.tmp
<llvm_src>/lib/Target/X86/X86.td -debug-only=regalloc-emitter
* RESULTS
Because of those ghost reg unit tablegen will segfault because it tries to
print the name of something that does not exist.
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