https://llvm.org/bugs/show_bug.cgi?id=24216
Bug ID: 24216
Summary: Incorrect VMX/Altivec Code Generation - Mis-using
splat instructions
Product: tools
Version: trunk
Hardware: PC
OS: Linux
Status: NEW
Severity: normal
Priority: P
Component: llc
Assignee: [email protected]
Reporter: [email protected]
CC: [email protected]
Classification: Unclassified
Created attachment 14629
--> https://llvm.org/bugs/attachment.cgi?id=14629&action=edit
tarball w/ .cl source, .ll source, .s output & Makefile
This bug causes the compiler to emit splat instructions which 'splat' the wrong
bytes from the source register. The issue is that the function
PPC::isSplatShuffleMask() in PPCISelLowering.cpp does not ensure that the
'splat' pattern found is requesting bytes that are aligned on an 'EltSize'
boundary. Therefore, the compiler emits splat instructions when it shouldn't;
the operation should be performed by a vperm or some other sequence of
instructions instead. Attached is an OpenCL-C function & the generated IR that
trigger this bug.
A simple fix would be to add this check in isSplatShuffleMask() with the
following line:
if (N->getMaskElt(0) % EltSize) return false;
This causes the VECTOR_SHUFFLE node to be lowered to a vperm inst instead. Is
there a better solution? Would a shift followed by a splat be preferred over a
vperm?
--
You are receiving this mail because:
You are on the CC list for the bug.
_______________________________________________
LLVMbugs mailing list
[email protected]
http://lists.cs.uiuc.edu/mailman/listinfo/llvmbugs
