Cache flush on arm provided via __ARM_NR_cacheflush(unsigned long start, unsigned long end, int flags) defined in ./arch/arm/kernel/traps.c. Flags are not used, providing 0 there.
Signed-off-by: Maxim Uvarov <[email protected]> --- .../kernel/syscalls/cacheflush/cacheflush01.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/testcases/kernel/syscalls/cacheflush/cacheflush01.c b/testcases/kernel/syscalls/cacheflush/cacheflush01.c index 9c02f0a..fae51b4 100644 --- a/testcases/kernel/syscalls/cacheflush/cacheflush01.c +++ b/testcases/kernel/syscalls/cacheflush/cacheflush01.c @@ -137,6 +137,14 @@ int main(int ac, char **av) } /* Invokes cacheflush() with proper parameters */ +#if defined(__arm__) + TEST(ltp_syscall(__ARM_NR_cacheflush, addr, addr + getpagesize(), 0)); + if (TEST_RETURN == 0) { + tst_resm(TPASS, "passed with no errno"); + } else { + tst_resm(TFAIL, "failed with unexpected errno"); + } +#else TEST(ltp_syscall(__NR_cacheflush, addr, getpagesize(), ICACHE)); if (TEST_RETURN == 0) { tst_resm(TPASS, "passed with no errno"); @@ -157,6 +165,7 @@ int main(int ac, char **av) } else { tst_resm(TFAIL, "failed with unexpected errno"); } +#endif cleanup(); tst_exit(); -- 1.7.9.5 ------------------------------------------------------------------------------ October Webinars: Code for Performance Free Intel webinars can help you accelerate application performance. Explore tips for MPI, OpenMP, advanced profiling, and more. Get the most from the latest Intel processors and coprocessors. See abstracts and register > http://pubads.g.doubleclick.net/gampad/clk?id=60134791&iu=/4140/ostg.clktrk _______________________________________________ Ltp-list mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/ltp-list
