* David Goulet ([email protected]) wrote: > -----BEGIN PGP SIGNED MESSAGE----- > Hash: SHA1 > > Hi everyone, > > This is an important change for libust so some questions are raised. > > The size alignment is of course different for each architecture. So, which > value > should be used here? (include/ust/core.h) : > > #define ____cacheline_aligned __attribute__((aligned(128))) > > Lib URCU define CACHE_LINE_SIZE to 128 and a previous discussion with Mathieu > Desnoyers was that typically, this value is hardcoded with the largest value > expected. In liburcu, the 128 size is based on Intel. Howerver, this is for > arch.h linked to arch_x86.h. > > So, we might actually change the default value for cache alignment base on > liburcu CACHE_LINE_SIZE definition since it is different for specific > architecture. (urcu/arch_*.h)
Yep, given that ust already depends on liburcu, it would make sense to re-use its CACHE_LINE_SIZE definition, which is already tuned on a arch-specific basis. Thanks, Mathieu > > For this modification, the test was done on an Intel i7, no decrease of > performance was registered but instead! scalability across multiple CPUs is > reached. So for 1 and 4 cpus, the per event time is quite the same and it's > not > the case right now. I've done multiple test for that. > > Discussion is now open! ;) > > Thanks to all! > David > > --- > > include/ust/core.h | 2 +- > > 1 files changed, 1 insertions(+), 1 deletions(-) > > > > diff --git a/include/ust/core.h b/include/ust/core.h > > index 8cedf98..1cffe52 100644 > > --- a/include/ust/core.h > > +++ b/include/ust/core.h > > @@ -122,7 +122,7 @@ static inline long IS_ERR(const void *ptr) > > /* ATTRIBUTES */ > > > > /* FIXME: define this */ > > -#define ____cacheline_aligned > > +#define ____cacheline_aligned __attribute__((aligned(128))) > > > > /* MATH */ > > > -----BEGIN PGP SIGNATURE----- > Version: GnuPG v1.4.9 (GNU/Linux) > > iEYEARECAAYFAkwyOQcACgkQSvfBSxa9hWMVegCgsldNomTLyKVCSipjdpEs1Qxi > 53MAnRGFbBWzcEGxQ2VzaGiDYEPVAdKa > =5RKD > -----END PGP SIGNATURE----- > > _______________________________________________ > ltt-dev mailing list > [email protected] > http://lists.casi.polymtl.ca/cgi-bin/mailman/listinfo/ltt-dev > -- Mathieu Desnoyers Operating System Efficiency R&D Consultant EfficiOS Inc. http://www.efficios.com _______________________________________________ ltt-dev mailing list [email protected] http://lists.casi.polymtl.ca/cgi-bin/mailman/listinfo/ltt-dev
