Hi,
I have some doubt about the value of #define CACHE_LINE_SIZE
(urcu/arch_x86.h) that is set to 128.
After some research and looking on my computer, the x86 architecture
seems to have most of the time 64 bytes size. On my i7 920, here's what
I have :
# getconf LEVEL1_DCACHE_LINESIZE
64
# cat /sys/devices/system/cpu/cpu0/cache/index0/coherency_line_size
64
Since the Intel NetBurst microarch., the Intel manual says 64 bytes also
and it has not changed apparently for Nehalem.
So, Mathieu, why 128 bytes? UST is using that, if it's the wrong value
here for x86, it could have an effect on cache pressure since 2 lines
are required for structure less then 64 bytes.
Thanks!
--
David Goulet
LTTng project, DORSAL Lab.
PGP/GPG : 1024D/16BD8563
BE3C 672B 9331 9796 291A 14C6 4AF7 C14B 16BD 8563
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