On 09/05/2011 05:12 PM, Mathieu Desnoyers wrote:
In userspace we can assume no accesses to write-combining memory occur,
> and also that there are no non-temporal load/stores (people would presumably
> write those with assembly or intrinsics and put appropriate lfence/sfence
> manually). So rmb and wmb are no-ops on x86.
What about memory barriers for DMA with devices ? For these, we might
want to define cmm_wmb/rmb and cmm_smp_wmb/rmb differently (keep the
fences for DMA accesses).
Yes, splitting wmb/rmb and smp_wmb/rmb makes sense.
Paolo
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