Title: E-mail signature
(from EVS)
Hello,
I was wondering if anyone already tried to implement a hardware
assisted checksum routine.
In our project, data flows through a FPGA wich can easily compute a
checksum while transferring. So as soon as the data are in our cpu
ram, we can also have associated checksum. Conceptually, it should be
easy to compute a TCP checksum by adding TCP (header + pseudo header
)related data to already computed raw data.
The problem is how to pass to lower layer (in the case of data going
out cpu to lan medium) the computed value ? Something like
tcp_write(pcb, buf, size, copy_mode, RAW_DATA_CHECKSUM) would be
perfect.
Do you have any thoughs on this question ?
(From Keiran)
You can only compute the checksum after you know what size fragment of
data you will be sending in each individual packet. You can't predict
this in advance or control it, so getting the FPGA to compute it would
not be very useful. E.g. if you call tcp_write() with a buffer of size
X, the packets on the network could be any fraction of X in length that
the stack finds convenient, and each would need a different checksum.
If you can pass the data through the FPGA after the stack has fragmented
it into packets, and get it to insert the checksum in the appropriate
place in the header, that might be useful, but it would then need to
buffer each packet rather perform it on the stream (as the checksum goes
at the beginning not the end) and so it will introduce some latency.
You basically then have a trade off between CPU use and latency, and
which is best will depend heavily on your hardware.
Hope that helps,
Kieran
It is common these days to have TCP/UDP/IP checksum assistance in
ethernet interface chips. This is a very appropriate place for the
checksum, since everything is ready for checksumming by the time it
gets to the chip.
The amount of preparation necessary in order to use this varies from
chip to chip. For that reason, driver level work is required. I
believe that FreeBSD and Linux driver interfaces have been modified to
accommodate the availability of checksumming services. It may be an
appropriate future consideration for lwIP.
If lwIP allowed checksumming services to be performed at the driver
level or beneath, then systems having special hardware - either in the
ethernet chip or some other FPGA - could be used.
--
Jim Gibbons
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[EMAIL PROTECTED]
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Gibbons and Associates, Inc.
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TEL: (408) 984-1441
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900 Lafayette, Suite 704, Santa Clara, CA
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FAX: (408) 247-6395
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