Allocate the pbuf large enough to handle worst case alignment and align its
payload after the allocation.  I do this on the PPC (8349) with Receive
Buffers that must be 64 byte-aligned.  I added an LWIP_ASSERT on the payload
& 0x3F being 0 to be sure I had it right.  I store the payload into the Rx
BD and keep a pointer to the pbuf in a static array whose index is the same
as the Rx BD.

 

Bill

 

From: [EMAIL PROTECTED]
[mailto:[EMAIL PROTECTED] On Behalf
Of Muhamad Ikhwan Ismail
Sent: Friday, May 09, 2008 9:10 AM
To: [email protected]
Subject: [lwip-users] Misalignment problems on PowerPC (little endian mode)

 


Hi,

I am interested in knowing if there is any other user of lwip who has
managed to implement lwip in PowerPC (little endian mode)
and got rid of the lil endian misalignment exceptions ? As lwip strips the
Ethernet header (14 bytes) the IP addr fields (4 bytes) in the IP header
sits on
a non-aligned address.My FEC is setup in a way that all received buffers are
stored directly into the pbufs instead of a temporary buffer to minimize
latency,
so the ethernet padding option does not really work for me. The FEC can only
save frames into addresses multiple of 16 only.

 So for me (as far as my knowledge limits me  :) ) there 2 other
possibilities left, one is packing the structure, or apply changes on the ip
address 
functions and macros so that it works with the ip address as 2 16 bit fields
instead of 1 32 bits field. Unfortunately I couldnt make structure packing 
work with my compiler (Wind River Compiler). I am interested in knowing if
anyone has done the same thing and mind sharing experience ? Any
thoughts,ideas and feedbacks would also be welcomed. 

ps: I have an alignment fixing subroutine, but then again we want to
minimize the latency.

Greetings and thanks in advance
Ikhwan Ismail
ABB STOTZ-KONTAKT GmbH
Heidelberg
Germany

 

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