Hi All, Thank you all for the response.
Like what you all have suggested, I have to port lwIP to my platform and needs to integrate it with the driver for SMSC 91C111. About the porting I got some suppport from the lwIP wiki and from there I can carry on. The solution looks possible as I have already interfaced my MAC/PHY chip with the microblaze and only pending thing are MAC/PHY device driver and lwIP. Thanks & Regards, Sreenath On Tue, Apr 14, 2009 at 8:26 PM, John Kennedy <[email protected]>wrote: > Sounds, like you will have to do your own LWIP port for your MAC/PHY > combination, you can't use the stock Xilinx LWIP library as is since as you > found it requires one of the Xilinx MACs. Basically you'll have to replace > the Xilinx MAC driver files with a driver for your specific MAC/PHY and then > modify the low level LWIP files that interface to the Xilinx MAC driver to > work with your MAC/PHY driver. This also requires that you can interface to > your MAC/PHY from microblaze i.e. you might also have to modify your FPGA > design to accomodate this. You might want to look at some of the ports > others have done that are available on the web. > > John > > > > *________________________________________* > *John Kennedy > * > > *Idaho Technology Inc. > *390 Wakara Way > Salt Lake City, UT 84108, USA > > USA: 1-800-735-6544 > Bus:+1 (801)736-6354 x448 > Fax:+1 (801)588-0507 > > www.idahotech.com > > -----Original Message----- > > > *From:* Sreenath S [mailto:[email protected]] > *Sent:* Tuesday, April 14, 2009 4:09 AM > *To:* [email protected] > *Subject:* [lwip-users] How to use Xilinx-lwIP with an external MAC core. > [ MAC + PHY chip SMSC 91C111 ] > > Hi All, > > > > I want to use lwIP with the external MAC + PHY chip [ SMSC 91C111 ] in my > board. > > Now I am able to access all SMSC 91C111 registers using epc (External > Peripheral Controller). > > However when I add lwIP support in the "Software Platform settings" and > try to compile, I gets the following error, > > > > ERROR:MDT - issued from TCL procedure "::sw_lwip_v3_00_a::lwip_drc" line > 12 > lwip () - No Ethernet MAC cores are addressable from processor > microblaze_0. > lwIP requires atleast one EMAC (xps_ethernetlite | xps_ll_temac) core. > > > > So the LwIP library come with the Xilinx EDK only works with Xilinx IP > cores (emac). > > Is there a possibility of using lwIP with external MAC core (external MAC > controller chip). ? > > > > In order to use the Xilinx EMAC IP cores, I require the support of > external PHY chip. > > However in my case, ethernet pins coming out are routed through SMSC > 91C111. > > So I don't have any other option other than use SMSC 91C111 along with > lwIP library. > > > > Please find the MHS and MSS files below for further reference and please > suggest a solution. > > > > Thanks & Regards, > > Sreenath > > > > *MHS* > > *------* > > > > # > ############################################################################## > # Created by Base System Builder Wizard for Xilinx EDK 9.2.02 Build EDK_ > Jm_SP2.3 > # Tue Apr 07 12:06:04 2009 > # Target Board: Custom > # Family: virtex5 > # Device: xc5vlx110 > # Package: ff1760 > # Speed Grade: -1 > # Processor: microblaze_0 > # System clock frequency: 100.00 MHz > # On Chip Memory : 64 KB > # > ############################################################################## > PARAMETER VERSION = 2.1.0 > > > PORT fpga_0_RS232_RX_pin = fpga_0_RS232_RX, DIR = I > PORT fpga_0_RS232_TX_pin = fpga_0_RS232_TX, DIR = O > PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000 > PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 0, SIGIS = RST > PORT xps_epc_ethernet_PRH_Data_pin = xps_epc_ethernet_PRH_Data, DIR = IO, > VEC = [0:31] > PORT xps_epc_ethernet_PRH_Wr_n_pin = xps_epc_ethernet_PRH_Wr_n, DIR = O > PORT xps_epc_ethernet_PRH_Rd_n_pin = xps_epc_ethernet_PRH_Rd_n, DIR = O > PORT xps_epc_ethernet_PRH_BE_pin = xps_epc_ethernet_PRH_BE, DIR = O, VEC= [ > 0:3] > PORT xps_epc_ethernet_PRH_ADS_pin = xps_epc_ethernet_PRH_ADS, DIR = O > PORT xps_epc_ethernet_PRH_Addr_pin = xps_epc_ethernet_PRH_Addr, DIR = O, > VEC = [0:15] > PORT xps_epc_ethernet_PRH_CS_n_pin = xps_epc_ethernet_PRH_CS_n, DIR = O, > VEC = [0:0] > PORT util_vector_logic_ethernet_BE_Res_pin = util_vector_logic_ethernet_ > BE_Res, DIR = O, VEC = [0:3] > PORT util_vector_logic_ethernet_DATACS_Res_pin = util_vector_logic_ > ethernet_DATACS_Res, DIR = O, VEC = [0:0] > PORT util_vector_logic_ethernet_RESET_Res_pin = util_vector_logic_ > ethernet_RESET_Res, DIR = O, VEC = [0:0] > PORT util_vector_logic_ethernet_AEN_Res_pin = util_vector_logic_ethernet_ > AEN_Res, DIR = O, VEC = [0:0] > PORT util_vector_logic_ethernet_ADS_Res_pin = util_vector_logic_ethernet_ > ADS_Res, DIR = O, VEC = [0:0] > PORT xps_epc_ethernet_PRH_Rdy_pin = xps_epc_ethernet_PRH_Rdy, DIR = I, > VEC = [0:0] > > > BEGIN microblaze > PARAMETER INSTANCE = microblaze_0 > PARAMETER C_INTERCONNECT = 1 > PARAMETER HW_VER = 7.00.b > PARAMETER C_DEBUG_ENABLED = 1 > BUS_INTERFACE DLMB = dlmb > BUS_INTERFACE ILMB = ilmb > BUS_INTERFACE DPLB = mb_plb > BUS_INTERFACE IPLB = mb_plb > BUS_INTERFACE DEBUG = microblaze_0_dbg > PORT MB_RESET = mb_reset > END > > BEGIN plb_v46 > PARAMETER INSTANCE = mb_plb > PARAMETER HW_VER = 1.00.a > PORT PLB_Clk = sys_clk_s > PORT SYS_Rst = sys_bus_reset > END > > BEGIN lmb_v10 > PARAMETER INSTANCE = ilmb > PARAMETER HW_VER = 1.00.a > PORT LMB_Clk = sys_clk_s > PORT SYS_Rst = sys_bus_reset > END > > BEGIN lmb_v10 > PARAMETER INSTANCE = dlmb > PARAMETER HW_VER = 1.00.a > PORT LMB_Clk = sys_clk_s > PORT SYS_Rst = sys_bus_reset > END > > BEGIN lmb_bram_if_cntlr > PARAMETER INSTANCE = dlmb_cntlr > PARAMETER HW_VER = 2.10.a > PARAMETER C_BASEADDR = 0x00000000 > PARAMETER C_HIGHADDR = 0x00007fff > BUS_INTERFACE SLMB = dlmb > BUS_INTERFACE BRAM_PORT = dlmb_port > END > > BEGIN lmb_bram_if_cntlr > PARAMETER INSTANCE = ilmb_cntlr > PARAMETER HW_VER = 2.10.a > PARAMETER C_BASEADDR = 0x00000000 > PARAMETER C_HIGHADDR = 0x00007fff > BUS_INTERFACE SLMB = ilmb > BUS_INTERFACE BRAM_PORT = ilmb_port > END > > BEGIN bram_block > PARAMETER INSTANCE = lmb_bram > PARAMETER HW_VER = 1.00.a > BUS_INTERFACE PORTA = ilmb_port > BUS_INTERFACE PORTB = dlmb_port > END > > BEGIN xps_uartlite > PARAMETER INSTANCE = RS232 > PARAMETER HW_VER = 1.00.a > PARAMETER C_BAUDRATE = 115200 > PARAMETER C_DATA_BITS = 8 > PARAMETER C_ODD_PARITY = 1 > PARAMETER C_USE_PARITY = 1 > PARAMETER C_SPLB_CLK_FREQ_HZ = 100000000 > PARAMETER C_BASEADDR = 0x84000000 > PARAMETER C_HIGHADDR = 0x8400ffff > BUS_INTERFACE SPLB = mb_plb > PORT RX = fpga_0_RS232_RX > PORT TX = fpga_0_RS232_TX > END > > BEGIN clock_generator > PARAMETER INSTANCE = clock_generator_0 > PARAMETER HW_VER = 1.00.a > PARAMETER C_EXT_RESET_HIGH = 1 > PARAMETER C_CLKIN_FREQ = 100000000 > PARAMETER C_CLKOUT0_FREQ = 100000000 > PARAMETER C_CLKOUT0_PHASE = 0 > PARAMETER C_CLKOUT0_GROUP = NONE > PORT CLKOUT0 = sys_clk_s > PORT CLKIN = dcm_clk_s > PORT LOCKED = Dcm_all_locked > PORT RST = net_gnd > END > > BEGIN mdm > PARAMETER INSTANCE = debug_module > PARAMETER HW_VER = 1.00.a > PARAMETER C_MB_DBG_PORTS = 1 > PARAMETER C_USE_UART = 1 > PARAMETER C_UART_WIDTH = 8 > PARAMETER C_BASEADDR = 0x84400000 > PARAMETER C_HIGHADDR = 0x8440ffff > BUS_INTERFACE SPLB = mb_plb > BUS_INTERFACE MBDEBUG_0 = microblaze_0_dbg > PORT Debug_SYS_Rst = Debug_SYS_Rst > END > > BEGIN proc_sys_reset > PARAMETER INSTANCE = proc_sys_reset_0 > PARAMETER HW_VER = 2.00.a > PARAMETER C_EXT_RESET_HIGH = 0 > PORT Slowest_sync_clk = sys_clk_s > PORT Dcm_locked = Dcm_all_locked > PORT Ext_Reset_In = sys_rst_s > PORT MB_Reset = mb_reset > PORT Bus_Struct_Reset = sys_bus_reset > PORT MB_Debug_Sys_Rst = Debug_SYS_Rst > END > > BEGIN xps_epc > PARAMETER INSTANCE = xps_epc_ethernet > PARAMETER HW_VER = 1.00.a > PARAMETER C_PRH0_ADDR_TSU = 12000 > PARAMETER C_PRH0_ADDR_TH = 12000 > PARAMETER C_PRH0_ADS_WIDTH = 20000 > PARAMETER C_PRH0_CSN_TSU = 12000 > PARAMETER C_PRH0_CSN_TH = 12000 > PARAMETER C_PRH0_WRN_WIDTH = 30000 > PARAMETER C_PRH0_WR_CYCLE = 100000 > PARAMETER C_PRH0_DATA_TSU = 20000 > PARAMETER C_PRH0_DATA_TH = 10000 > PARAMETER C_PRH0_RDN_WIDTH = 30000 > PARAMETER C_PRH0_RD_CYCLE = 100000 > PARAMETER C_PRH0_DATA_TOUT = 10000 > PARAMETER C_PRH0_DATA_TINV = 20000 > PARAMETER C_PRH0_RDY_TOUT = 20000 > PARAMETER C_PRH0_RDY_WIDTH = 100000 > PARAMETER C_PRH_MAX_AWIDTH = 16 > PARAMETER C_PRH0_AWIDTH = 16 > PARAMETER C_PRH0_SYNC = 0 > PARAMETER C_PRH0_BASEADDR = 0x84500000 > PARAMETER C_PRH0_HIGHADDR = 0x8457ffff > BUS_INTERFACE SPLB = mb_plb > PORT PRH_Data = xps_epc_ethernet_PRH_Data > PORT PRH_Wr_n = xps_epc_ethernet_PRH_Wr_n > PORT PRH_Rd_n = xps_epc_ethernet_PRH_Rd_n > PORT PRH_BE = xps_epc_ethernet_PRH_BE > PORT PRH_ADS = xps_epc_ethernet_PRH_ADS > PORT PRH_Addr = xps_epc_ethernet_PRH_Addr > PORT PRH_CS_n = xps_epc_ethernet_PRH_CS_n > PORT PRH_Rdy = xps_epc_ethernet_PRH_Rdy > END > > BEGIN util_vector_logic > PARAMETER INSTANCE = util_vector_logic_ethernet_BE > PARAMETER HW_VER = 1.00.a > PARAMETER C_OPERATION = not > PARAMETER C_SIZE = 4 > PORT Op1 = xps_epc_ethernet_PRH_BE > PORT Res = util_vector_logic_ethernet_BE_Res > END > > BEGIN util_vector_logic > PARAMETER INSTANCE = util_vector_logic_ethernet_DATACS > PARAMETER HW_VER = 1.00.a > PARAMETER C_OPERATION = or > PARAMETER C_SIZE = 1 > PORT Op1 = net_vcc > PORT Op2 = net_vcc > PORT Res = util_vector_logic_ethernet_DATACS_Res > END > > BEGIN util_vector_logic > PARAMETER INSTANCE = util_vector_logic_ethernet_RESET > PARAMETER HW_VER = 1.00.a > PARAMETER C_OPERATION = or > PARAMETER C_SIZE = 1 > PORT Op1 = mb_reset > PORT Op2 = mb_reset > PORT Res = util_vector_logic_ethernet_RESET_Res > END > > BEGIN util_vector_logic > PARAMETER INSTANCE = util_vector_logic_ethernet_AEN > PARAMETER HW_VER = 1.00.a > PARAMETER C_OPERATION = or > PARAMETER C_SIZE = 1 > PORT Op1 = net_gnd > PORT Op2 = net_gnd > PORT Res = util_vector_logic_ethernet_AEN_Res > END > > BEGIN util_vector_logic > PARAMETER INSTANCE = util_vector_logic_ethernet_ADS > PARAMETER HW_VER = 1.00.a > PARAMETER C_OPERATION = or > PARAMETER C_SIZE = 1 > PORT Op1 = net_gnd > PORT Op2 = net_gnd > PORT Res = util_vector_logic_ethernet_ADS_Res > END > > > > *MSS* > > *------ * > > > > PARAMETER VERSION = 2.2.0 > > > BEGIN OS > PARAMETER OS_NAME = standalone > PARAMETER OS_VER = 1.00.a > PARAMETER PROC_INSTANCE = microblaze_0 > PARAMETER STDIN = RS232 > PARAMETER STDOUT = RS232 > END > > > BEGIN PROCESSOR > PARAMETER DRIVER_NAME = cpu > PARAMETER DRIVER_VER = 1.11.a > PARAMETER HW_INSTANCE = microblaze_0 > PARAMETER COMPILER = mb-gcc > PARAMETER ARCHIVER = mb-ar > END > > > BEGIN DRIVER > PARAMETER DRIVER_NAME = bram > PARAMETER DRIVER_VER = 1.00.a > PARAMETER HW_INSTANCE = dlmb_cntlr > END > > BEGIN DRIVER > PARAMETER DRIVER_NAME = bram > PARAMETER DRIVER_VER = 1.00.a > PARAMETER HW_INSTANCE = ilmb_cntlr > END > > BEGIN DRIVER > PARAMETER DRIVER_NAME = generic > PARAMETER DRIVER_VER = 1.00.a > PARAMETER HW_INSTANCE = lmb_bram > END > > BEGIN DRIVER > PARAMETER DRIVER_NAME = uartlite > PARAMETER DRIVER_VER = 1.12.a > PARAMETER HW_INSTANCE = RS232 > END > > BEGIN DRIVER > PARAMETER DRIVER_NAME = generic > PARAMETER DRIVER_VER = 1.00.a > PARAMETER HW_INSTANCE = clock_generator_0 > END > > BEGIN DRIVER > PARAMETER DRIVER_NAME = uartlite > PARAMETER DRIVER_VER = 1.12.a > PARAMETER HW_INSTANCE = debug_module > END > > BEGIN DRIVER > PARAMETER DRIVER_NAME = generic > PARAMETER DRIVER_VER = 1.00.a > PARAMETER HW_INSTANCE = proc_sys_reset_0 > END > > BEGIN DRIVER > PARAMETER DRIVER_NAME = generic > PARAMETER DRIVER_VER = 1.00.a > PARAMETER HW_INSTANCE = xps_epc_ethernet > END > > > BEGIN LIBRARY > PARAMETER LIBRARY_NAME = lwip > PARAMETER LIBRARY_VER = 3.00.a > PARAMETER PROC_INSTANCE = microblaze_0 > PARAMETER api_mode = SOCKET_API > PARAMETER pbuf_debug = true > PARAMETER sys_debug = true > PARAMETER netif_debug = true > PARAMETER tcp_debug = true > PARAMETER ip_debug = true > PARAMETER lwip_debug = true > PARAMETER lwip_stats = true > END > > *________________________________________* > CONFIDENTIALITY NOTICE: This E-mail and any attachments are confidential > information of the sender and are for the exclusive use of the intended > recipient. If you are not the intended recipient, be aware that any > disclosure, copying, distribution, or use of this E-mail or any attachment > is prohibited. If you have received this E-mail in error, please notify us > immediately by returning it to the sender and delete this copy from your > system. Thank you for your cooperation. > > > > _______________________________________________ > lwip-users mailing list > [email protected] > http://lists.nongnu.org/mailman/listinfo/lwip-users >
_______________________________________________ lwip-users mailing list [email protected] http://lists.nongnu.org/mailman/listinfo/lwip-users
