"Stephane Lesage" <[email protected]> wrote: > I need 32 bytes alignement on Blackfin for L1 cache > and even 128 bytes on C674x for L2 cache. > > I just add this in my cc.h: > > // PBUF_POOL needs to be aligned to cache line size > #ifndef __cplusplus > extern u8_t memp_memory_PBUF_POOL_base[] __attribute__ ((aligned (32))); > #endif > > And in my lwipopts.h: > > #define PBUF_POOL_BUFSIZE 1520 > // + sizeof(pbuf) = 1536 = 48 cache lines
But then struct pbuf is still only 16 bytes long, so payload might start in the middle of a 32-byte border, which leads to faults when flushing cache (since the struct pbuf members are still used cached) or am I wrong there? > But I agree it could be easier with something like: > #define PBUF_ALIGNMENT 32 That's what I imagined (only with another name maybe). Simon -- Empfehlen Sie GMX DSL Ihren Freunden und Bekannten und wir belohnen Sie mit bis zu 50,- Euro! https://freundschaftswerbung.gmx.de _______________________________________________ lwip-users mailing list [email protected] https://lists.nongnu.org/mailman/listinfo/lwip-users
