Can't help you with IAR, but maybe you can tell your processor to handle
unaligned access. Depending on your CPU type (following example is
Cortex-A9, Altera Cyclone V) your startup code may look like this (gcc asm):
Reset_Handler:
MRC p15, 0, r0, c1, c0, 0 /* ; Read CP15 System Control
register */
BIC r0, r0, #(0x1 << 12) /* ; Disable I Cache */
BIC r0, r0, #(0x1 << 11) /* ; Disable branch
predictor */
BIC r0, r0, #(0x1 << 2) /* ; Disable D Cache */
BIC r0, r0, #(0x1 << 1) /* ; Disable Alignment checks */
BIC r0, r0, #(0x1 << 0) /* ; Disable MMU */
MCR p15, 0, r0, c1, c0, 0 /* ; Setup mode */
Ciao
Dirk
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