On 12.03.2018 22:27, Brian dina wrote:

I am using a Xilinx board with a Microblaze processor to run the echo_server example code.  I noticed that if I send 8 bytes at one second intervals that the delay from packets sent and packets received begins to grow.  I don't feel like its a memory leak but have read online other people run into the same issue, with different boards, but so far Xilinx has not responded to mine or others who have had the same issue.  I feel there must be something I'm missing in how the BSP sets the drivers for the lwip.  Could anyone maybe guide me or tell me why there would be an increasing delay.

This looks like one of the issues in timers I have seen, although it's worse than what I would have expected. Current git master code should not have any problems there any more. Does Xilinx still ship 1.4.1 (which is more than 7 years old by now)? If so, why don't the ones who pay them money make them use up-to-date source? If they run into problems, tell them to come here and get support in upgrading the stack :-)


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