Orientation is correct. I suppose I might have fried it before. Funny thing is that I measured proper 3.3v at the jtag header yesterday but didn't have my programmer handy to flash it. Today I tried to program the CPLD and it smoked. I must have just buggered something up good. Or, like you said, dud part. Dunno.
I need to order more parts, so I'll try again later. No idea of the vreg is still good or not either. It will delay my work but oh well. I figure someone else will report success with the new board design before I get around to it, anyway. :-/ -Josh On Wed, Oct 18, 2017 at 4:25 PM, Stephen Adolph <[email protected]> wrote: > I can try to measure it later today for you. > > On Wed, Oct 18, 2017 at 4:24 PM, Stephen Adolph <[email protected]> > wrote: >> >> either the chip is a dud, or you have soldered it down in the wrong >> orientation (which is kinda easy to do)... Do you have more CPLDs? >> >> On Wed, Oct 18, 2017 at 4:22 PM, Josh Malone <[email protected]> >> wrote: >>> >>> Thanks for the leads. >>> >>> I removed the CPLD and the resistance from 3v3 to gnd went to open; >>> repopulated it and it went to 3-ohms. Dunno what to try next. Maybe >>> put the same CPLD back on an original REX board (non-castellated) and >>> see what happens. But, I'd *really* love for someone to measure the >>> resistance on a known-good REX board and let me know what it should >>> be. Assuming the CPLD draws <= 1ma (datasheet says 17uA standby), R >>> should be over ~3k. >>> >>> -Josh >> >> >
