Hey Rob,
Sorry for the delayed response ... your message ended up in my SPAM
folder for some reason, along with the other responses on this thread.
I must have hit the wrong key and marked the thread as SPAM accidentally
or something.
After running my simulation yesterday and sending the email, I dug into
the design I had done to remind myself. Turns out I had done QUITE A
BIT of work back in 2012. I had extended the 8085 CPU with not only
relative branch opcode, but also extended it's memory range to 16MB.
This was done by:
a. Adding an 8-bit "page" register for each of the 16-bit register
pairs (BC, DE, HL and PC).
b. Added an opcode to set the "page" register for those 16-bit reg
pairs.
c. Adding opcodes for long jump operations: LJMP, LCALL, LRET
d. Changing the INT sources to perform LONG jump back to page zero
of the ROM.
e. Patching the main M100 SYSTEM ROM to support LRET from the ISRs.
f. Adding a memory map peripheral that allows memory from the 16-meg
space to be mapped to the base 64K space in 8K chunks (or maybe it was
4K chunks).
g. Wrote assembly code to test all of the extended OPCODES, then
setup the memory mapper with the main PATCHED ROM located at physical
address 0x30000 (mapped to the lower 64K) just to test it out.
h. Wrote an LCD handler that can accept standard M100 LCD signals
from both 8085Ext CPU *and* an ARM/RISC-V CPU at the same time. This
module has memory for both interfaces and saves the state in that memory
if the other CPU has control of the physical LCD. Then when a Keyboard
hotkey is pressed (CTRL-SHIFT-GRAPH 1 or CTRL-SHIFT-GRAPH-2), the
module will updated the physical LCD from the saved up SRAM image using
an internal state machine.
So the screenshot output from the simulation I posted yesterday was all
of that running!
And actually, I would really like to join your "group of engineers" and
help with this! I have a whole collection of FPGA boards at my disposal
here at home:
Arty-35T (Xilinx Artix-7 FPGA)
CMOD-A7 (Xilinx Artix-7 FPGA)
Mercury (Xilinx Spartan-6 FPGA)
Digilent NEXYS-3 (Xilinx Spartan-6 FPGA)
miniSpartan-6+ (Xilinx Spartan-6 FPGA)
DE0-NANO (Altera Cyclone IV FPGA)
Brevia2 (Lattice XP2-5E FPGA)
Currently my favorite is the CMOD-A7 because it is small and has easy to
use 512K Byte SRAM, is a breadboard form factor and is readily
available. But it is not 5V compliant, so that would need to be addressed.
The Arty-35T has more memory, but is DDR3 and a bit more difficult to
work with. But the board has Ethernet and other peripherals that the
CMOD-A7 doesn't.
I also see there is a Mercury-2 board now with an Artix-7 FPGA, on-board
SRAM and on-board 5V I/O translators. But I think this company is a
one-man shop and he just makes them based on sales, so I don't know
about consistency of availability. But I really like the Mercury-1
boards I have.
I will put stuff together on a github site and also create a block
diagram of what I have.
Ken
On 5/22/21 2:18 PM, Rob Messer wrote:
Ken,
That is awesome! I am admittedly a mechanical engineer and I took one
semester of computer engineering and VHDL programming and changed
majors (I was more of a beer drinker than D&D guy). In any event I
will rope in some colleagues and badger them with questions. Another
question is whether there are LCD screens close to what the Model 100
had still available (240X64) with similar dimensions. It think backlit
would be great.
I have been really saddened to see fewer and fewer Model 100s on Ebay.
I also think the machine could be very useful still. I am thinking
about people who want to work without distraction of the internet and
have some basic capabilities. Imagine adding some minor features like
bluetooth file transfer and an SD card slot, that would make this a
very useful device. It will be the model 104 :)
If you want to share this on Github that would be great! I will be
sure to update you on the progress!
BR
/RGM
On Sat, May 22, 2021 at 9:44 PM Ken Pettit <[email protected]
<mailto:[email protected]>> wrote:
Hey Rob,
I have an RTL design I worked on YEARS ago where I was trying to
get the
Model 100 in an FPGA along with some extensions. It was back when
there
was a lot of talk on the list about a Model 401. For those who
weren't
around then or don't recall, the Model 401 was something that was
discussed around April Fools day (thus the number 401) about an
updated
Model 100.
I actually had this running somewhat on an Actel Igloo FPGA at that
time, though not fully. I believe I had extended the 8085
instruction
set to add relative jump and branch opcodes using the "MOV A,A", "MOV
B,B" etc. opcodes which are basically useless and not used in the
M100
ROM. I was also planning at that time to have a 2-processor system
where the LCD and Keyboard would be shared by both the extended
8085 and
an ARM core. The keyboard controller I wrote detects a hotkey escape
sequence to connect the LCD and keyboard to either the ARM
interface or
the 8085 interface.
I just re-ran my RTL simulation and I see that it is at least running
and generating an output on the RTL testbench LCD monitor that I
wrote.
This LCD monitor in the testbench monitors all LCD writes and outputs
"pixels" as X'x to a Linux /dev/pty device. Then with minicom
connected
using Linux socat, I can see what the emulation is sending to the
LCD.
I have attached a snapshot of the output of the simulation (the
dots are
actually very small X's, just zoomed out so it's like a 3-point
font on
minicom or something). You can see the minicom status line at the
bottom
in a very small font. I can see the time isn't advancing, so maybe
something not quite right with the clock chip RTL (uPD1990.v).
If you would like to use this RTL as a starting point, I'm happy
to post
it to github and give you a link. The files in this design are:
-rw-rw-r-- 1 kpettit users 4108 Apr 16 2012 armspi.v
-rw-rw-r-- 1 kpettit users 97936 Apr 12 2012 cpu8085.v
-rw-rw-r-- 1 kpettit users 2468 May 8 2016 fifo1kx13sram.v
-rw-r--r-- 1 kpettit users 1531 May 9 2016 hvsync_generator.v
-rw-rw-r-- 1 kpettit users 19422 Mar 31 2012 im6402.v
-rw-rw-r-- 1 kpettit users 8344 May 6 2016 keymap.v
-rw-rw-r-- 1 kpettit users 12032 May 5 2016 keyscan.v
-rw-rw-r-- 1 kpettit users 40316 May 7 2016 lcd.v
-rw-rw-r-- 1 kpettit users 687 May 9 2016 m100rom.v
-rw-rw-r-- 1 kpettit users 6383 Apr 13 2012 mapper.v
-rw-rw-r-- 1 kpettit users 16475 May 7 2016 model401.v
-rw-r--r-- 1 kpettit users 7842 May 5 2016 nr5_tx8n.vhd
-rw-rw-r-- 1 kpettit users 6161 May 4 2016 nr5_uart.v
-rw-rw-r-- 1 kpettit users 5947 Apr 7 2012 pio8155.v
-rw-rw-r-- 1 kpettit users 1825 Mar 23 2012 ramCore512.v
-rw-rw-r-- 1 kpettit users 1836 Apr 11 2012 ramCore512x9.v
-rw-rw-r-- 1 kpettit users 9971 Apr 15 2012 socTop.v
-rw-rw-r-- 1 kpettit users 1036 May 9 2016 sram32k.v
-rw-rw-r-- 1 kpettit users 1114 May 7 2016 sram512.v
-rw-rw-r-- 1 kpettit users 1116 May 8 2016 sram512x9.v
-rw-r--r-- 1 kpettit users 9053 May 5 2016 uart_rx8n.vhd
-rw-rw-r-- 1 kpettit users 10794 Apr 7 2012 uPD1990.v
Ken
On 5/22/21 11:22 AM, Rob Messer wrote:
> I have followed this email list for a years and I have never
asked a
> question...but here goes! I am sitting here with my model 100 and I
> had an idea to 3D print a replica case and get my hands on an
LCD and
> mechanical keyboard and try to faithfully reproduce the Model
100 with
> simple additions. I have enlisted a few friends (we are all
> engineers)... I was wondering of anyone knows of an FPGA
> implementation of the Model 100 hardware? I want to make a fairly
> faithful reproduction short of using an 80C85.
>
> Thanks!
>
> --
> Robert Messer
> BARA Sweden
>
>
--
Robert Messer
Palisandergatan 13
Bara Sverige 23040
Tel: 01146708901871
www.linkedin.com/in/ <http://www.linkedin.com/in/>robert-messer-a3833b4
