On 11/14/22 11:47, Georg Käter wrote:
Hello together,
my Tandy 200 (European version, build in 1985) uses main PCB
#-PLX178AHIX. This board accepts
standard UV-eraseable EPROM 27C256 (32kB) and 27C64 (8kB) 150ns type w/o
any modification.
Maybe there are other revisions of PCB with different EPROM pinout I´m
not aware of.
In a conversation off-list just now I think we just figured out why it
works.
I'll just describe verbally but to follow along and check the work, the
reference material you'll need are the service manual for 200 to get the
schematic for the 200, and the datasheets for HN61364, and 27C64. All
easily googled. And in the 200 schematic you're looking at the M13 and
M15 positions (top-right corner), and one gate on M29 that combines 2
signals into one pin on M15.
To start, all else being equal,
* both chips get their /CS at the same time from the same /RD line from
the 200
* both chips, (in a sense, if you count the OR gate on M29 as part of
M15) get their /OE at the same time from /BANK1 from the 200
* A15 ends up interlocking the two chips so that when one is active the
other is inactive. When A15 is low, only M15 is enabled, and when A15 is
high only M13 is enabled. This assumes that the pin labelled /CE1 is
really an active high not an active low, and we CAN assume that, because
all other pins on both chips are not up for any kind of debate, they are
known and certain and not ambiguous. If pin 27 on M13 were actually
active-low, then both chips would be active at the same time.
(The pin names on M13 are a bit confising because for some reason the
200 schematic labels the 3 OE pins as /CE0 /CE1 /CE2. But they are
really OE pins not CE pins. The /CE pin is /CS, and for this discussion
I'm calling the others /OE0, OE1, and /CE2. OE1 is really active-high so
that's yet another correction.)
So the tldr for the normal case with original parts is:
A15 low=M15 high=M13
Now with a standard 27C64:
* pin 1 is NC from the socket, which means VPP is floating. That is bad
in general, but you get away with it in this case because it's not a
normal input but a VPP that needs a much higher voltage than vcc or any
voltage any other pin ever sees. Since no pin anywhere on the chip ever
sees anything outside the range of gnd to vcc, then a flapping input may
flap, but shouldn't be able to float any higher than vcc, and vcc is
just fine. Ideally we want that pin nailed to vcc even. It means we can
essentially ignore VPP, and ignore the write implications of /WE. We
can't ignore /WE, but we can ignore the *write* implications. It can
never write, regardless what state /WE is in, regardless what state any
other pins are in.
* /OE has the same /BANK1 as the /OE on M15 (via M29)
* A15 is on /WE
So, it's just down to answering: What happens when A15 is high, and when
it's low, when the states of the other pins are all VPP<=vcc, /CE low,
/OE low?
A15 low -> /WE low, which is technically undefined behavior being low at
the same time as /OE, but apparently overrides /OE and prevents output.
/CE and /OE are both low so it wants to output data, but /WE blocks it,
and yet, /WE doesn't write either because of missing VPP.
And, that is what we happen to want. Above in the stock case, A15 low =
M13 disabled.
A15 high -> /WE disabled, /OE is low so the chip outputs, and again that
is what we want. Above, A15 high = M13 active.
So /WE without VPP is kind of being abused into acting as a secondary
active-high OE, which is what the HN61364 has explicitly on that pin.
(well, it's not that HN61364 has pin 27 = active high OE1, it's that the
pin is configurable and the mask programming happens to have programmed
that pin to be active high in this case.)
So, it's not merely seeming to work by luck and maybe it's just lucky
that you don't get data corruption because of chance and statistics, but
really working, like you will never get data corruption because the
logic rules don't allow for it.
And it doesn't hurt the 200 electrically either. There are no outputs
fighting each other or anything like that. Electrically fine.
Myself I would lift out pin 1 and bodge it to pin 28 on all 27xxx chips
put in place of mask roms, but it's not really necessary.
Oh the HN61364 has one other non-standard pin, but you can ignore that
too. Pin 26 is a 3rd active-low OE, and tied to gnd in the socket, so
it's not used by the 200 and hard wired to just be enabled at all times,
meaning you can pretend it doesn't exist. And it's a NC pin on a 27C64,
so the gnd doesn't matter and so again you can ignore it.
And that's that. I think. Mystery solved?
--
bkw
Regards
Georg
Georg Käter
Gangolfsweg 44
D-52076 Aachen
Tel. : +49 2408 7194987
Fax. : +49 2408 7196758
Mobil : +49 171 4839954
E-Mail :
[email protected]
<mailto:[email protected]>
========== Ihre Nachricht ==========================================
*von* : Brian K. White <[email protected]>
*gesendet* : Montag, 14. November 2022, 16:24
*an* : [email protected]
*Betreff* : [M100] custom key mapping generator for Tandy 200
__________ Originalnachricht _______________________________________
On 11/14/22 10:11, Brian K. White wrote:
On 11/14/22 09:12, Brian White wrote:
The datasheet says to rest vpp at vcc. Most do, even if
elsewhere they >> also say that writing is disabled as long
as vpp is below vpp and the >> only low limit is pretty much
the same as for any other pin, like 0.5 >> or 0.7 below vcc.
derp I mean the low limit is a little below GND or VSS not VCC.
Although a Microchip 27C64 datasheet I happen to be looking at
at the > moment does actually say the vpp read voltage is min
vcc-0.7, max vcc.
More derp, I obviously confused VPP with /WE there.
But pin 27, being /WE (/PGM), still needs to be held at VCC not GND,
although theoretically any writes should still fail without VPP, but
still, you just hold /WE at VCC for reads.
__________ Ende Originalnachricht __________________________________
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bkw
