I believe SimpleScalar accesses the icache for each instruction, while
M5's FullCPU only accesses the icache once per cycle for all the
instructions it is fetching that are in the same icache line.
(Depending on how aggressive your fetch model is, M5 will access the
icache multiple times in a cycle, but only if it's fetching a set of
instructions that span icache blocks.) I wouldn't be surprised if the
number of icache accesses in SimpleScalar is larger by a factor of about
the issue width of the machine.
Steve
Jos Delbar wrote:
Hey,
I am trying to tune the configurations of M5 and sim-outorder to achieve
similar IPC results for uniprocessor simulations. Using more or less
identical processor configurations (as good as possible considering the
differences between the two simulators), identical cache configurations,
etc., I am getting "reasonable" results. One statistic is bothering me
though, and that is the amount of L1 icache lookups. For an identical
benchmark, sim-outorder reports +/- twice as many icache lookups as M5. L1
data and L2 unified cache lookups only differ a few percent.
Does anyone have an idea where this huge difference is coming from?
Thanks,
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